SI5323 Datasheet, PDF (10/16 Pages) Silicon Laboratories – PIN-PROGRAMMABLE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5323
Pin #
23
22
Pin Name
BWSEL1
BWSEL0
27
FRQSEL3
26
FRQSEL2
25
FRQSEL1
24
FRQSEL0
29
CKOUT1–
28
CKOUT1+
33
SFOUT0
30
SFOUT1
34
CKOUT2–
35
CKOUT2+
36
GND
PAD
NC
GND
Table 3. Si5323 Pin Descriptions (Continued)
I/O Signal Level
Description
I
3-Level Bandwidth Select.
Three level inputs that select the DSPLL closed loop band-
width. Detailed operations and timing characteristics for
these pins may be found in the Any-Rate Precision Clock
Family Reference Manual.
I
3-Level Multiplier Select.
Three level inputs that select the input clock and clock multi-
plication ratio, depending on the FRQTBL setting. Consult
the Any-Rate Precision Clock Family Reference Manual or
DSPLLsim configuration software for settings, both available
for download at www.silabs.com/timing.
O
Multi
Clock Output 1.
Differential output clock with a frequency selected from a
table of values. Output signal format is selected by SFOUT
pins. Output is differential for LVPECL, LVDS, and CML com-
patible modes. For CMOS format, both output pins drive
identical single-ended clock outputs.
I
3-Level Signal Format Select.
Three level inputs that select the output signal format (com-
mon mode voltage and differential swing) for both CKOUT1
and CKOUT2.
SFOUT[1:0]
Signal Format
HH
Reserved
HM
Reserved
HL
CML
MH
LVPECL
MM
Reserved
ML
LVDS
LH
CMOS
LM
Tristate/Sleep
LL
Reserved
O
—
GND
Multi
—
Supply
Clock Output 2.
Differential output clock with a frequency selected from a
table of values. Output signal format is selected by SFOUT
pins. Output is differential for LVPECL, LVDS, and CML com-
patible modes. For CMOS format, both output pins drive
identical single-ended clock outputs.
No Connect.
These pins must be left unconnected for normal operation.
Ground Pad.
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
10
Preliminary Rev. 0.2