SI5323 Datasheet, PDF (8/16 Pages) Silicon Laboratories – PIN-PROGRAMMABLE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5323
Pin #
5, 10,
32
7
6
8, 31
9
11
15
12
13
14
Pin Name
V_DD
XB
XA
GND
AUTOSEL
RATE0
RATE1
CKIN2+
CKIN2–
DBL2_BY
Table 3. Si5323 Pin Descriptions (Continued)
I/O
V_DD
I
GND
I
I
I
I
Signal Level
Description
Supply
Supply.
The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass
capacitors should be associated with the following V_DD pins:
5
0.1 µF
10
0.1 µF
32
0.1 µF
A 1.0 µF should be placed as close to device as is practical.
Analog
External Crystal or Reference Clock.
External crystal should be connected to these pins to use
internal oscillator based reference. If external reference is
used, apply reference clock to XA input and leave XB pin
floating. External reference must be from a high-quality clock
source (TCXO, OCXO). Frequency of crystal or external
clock is set by the RATE pin.
Supply
Ground.
Must be connected to system ground. Minimize the ground
path impedance for optimal performance of this device.
3-Level
Manual/Automatic Clock Selection.
Three level input that selects the method of input clock selec-
tion to be used.
L = Manual
M = Automatic non-revertive
H = Automatic revertive
3-Level
External Crystal or Reference Clock Rate.
Three level input that selects the type and rate of external
crystal or reference clock to be applied to the XA/XB port.
RATE[1:0]
LM
= 38.88 MHz external clock
MM
= 114.285 MHz 3rd OT Crystal
HH
= Converts part to Si5322
All Others = Reserved
Clock Input 2.
Differential input clock. This input can also be driven with a
single-ended signal. Input frequency selected from a table of
values. The same frequency must be applied to CKIN1 and
CKIN2.
3-Level
Output 2 Disable/Bypass Mode Control.
Controls enable of CKOUT2 divider/output buffer path and
PLL bypass mode.
L = CKOUT2 enabled
M = CKOUT2 disabled
H = Bypass mode with CKOUT2 enabled
8
Preliminary Rev. 0.2