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SI5323 Datasheet, PDF (2/16 Pages) Silicon Laboratories – PIN-PROGRAMMABLE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR | |||
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Si5323
Table 1. Performance Specifications
(VDD = 1.8, 2.5, or 3.3 V ±10%, TA = â40 to 85 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
Temperature Range
TA
Supply Voltage
VDD
â40
25
85
ºC
2.97
3.3
3.63
V
2.25
2.5
2.75
V
1.62
1.8
1.98
V
Supply Current
IDD
fOUT = 622.08 MHz
Both CKOUTs enabled
LVPECL format output
251
279
mA
CKOUT2 disabled
â
217
243
mA
fOUT = 19.44 MHz
â
Both CKOUTs enabled
CMOS format output
204
234
mA
CKOUT2 disabled
â
194
220
mA
Tristate/Sleep Mode
TBD
TBD
mA
Input Clock Frequency
(CKIN1, CKIN2)
Output Clock Frequency
(CKOUT1, CKOUT2)
CKF
CKOF
Input frequency and clock
multiplication ratio pin-select-
able from table of values
using FRQSEL and FRQTBL
settings. Consult Silicon Lab-
oratories configuration soft-
ware DSPLLsim or Any-Rate
Precision Clock Family Ref-
erence Manual at
www.silabs.com/timing for table
selections.
0.008
0.008
â
707.35 MHz
â
1049.76 MHz
Input Clocks (CKIN1, CKIN2)
Differential Voltage Swing CKNDPP
Common Mode Voltage CKNVCM
1.8V ±10%
2.5V ±10%
0.25
â
0.9
â
1.0
â
1.9
VPP
1.4
V
1.7
V
3.3V ±10%
1.1
â
1.95
V
Rise/Fall Time
Duty Cycle
CKNTRF
CKNDC
20â80%
Whichever is less
â
â
11
ns
40
â
60
%
50
â
â
ns
Output Clocks (CKOUT1, CKOUT2)
Common Mode
Differential Output Swing
Single Ended Output
Swing
VOCM
VOD
VSE
LVPECL
100 ⦠load
line-to-line
VDD â 1.42
â
VDD â 1.25 V
1.1
â
1.9
V
0.5
â
0.93
V
Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing.
2
Preliminary Rev. 0.2
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