SI5323 Datasheet, PDF (7/16 Pages) Silicon Laboratories – PIN-PROGRAMMABLE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

2. Pin Descriptions: Si5323
Si5323
36 35 34 33 32 31 30 29 28
RST 1
27 FRQSEL3
FRQTBL 2
26 FRQSEL2
C1B 3
25 FRQSEL1
C2B 4
VDD 5
XA 6
GND
Pad
24 FRQSEL0
23 BWSEL1
22 BWSEL0
XB 7
21 _{CS_CA}
GND 8
20 INC
AUTOSEL 9
19 DEC
10 11 12 13 14 15 16 17 18
Pin assignments are preliminary and subject to change.
Table 3. Si5323 Pin Descriptions
Pin #
1
Pin Name
RST
2
FRQTBL
3
C1B
4
C2B
I/O Signal Level
Description
I
LVCMOS External Reset.
Active low input that performs external hardware reset of
device. Resets all internal logic to a known state. Clock out-
puts are tristated during reset. After rising edge of RST sig-
nal, the Si5323 will perform an internal self-calibration.
This pin has a weak pull-up.
I
3-Level Frequency Table Select.
Selects SONET/SDH, datacom, or SONET/SDH to datacom
frequency table.
L = SONET/SDH
M = Datacom
H = SONET/SDH to Datacom
This pin has a weak pull-down.
O
LVCMOS CKIN1 Loss of Signal.
Active high loss-of-signal indicator for CKIN1. Once trig-
gered, the alarm will remain active until CKIN1 is validated.
0 = CKIN1 present
1 = LOS on CKIN1
O
LVCMOS CKIN2 Loss of Signal.
Active high loss-of-signal indicator for CKIN2. Once trig-
gered, the alarm will remain active until CKIN2 is validated.
0 = CKIN2 present
1 = LOS on CKIN2
Preliminary Rev. 0.2
7