SI5323 Datasheet, PDF (6/16 Pages) Silicon Laboratories – PIN-PROGRAMMABLE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5323
1. Functional Description
The Si5323 is a jitter-attenuating precision clock
multiplier for high-speed communication systems,
including SONET OC-48/OC-192, Ethernet, and Fibre
Channel. The Si5323 accepts dual clock inputs ranging
from 8 kHz to 707 MHz and generates two frequency-
multiplied clock outputs ranging from 8 kHz to
1050 MHz. The two input clocks are at the same
frequency and the two output clocks are at the same
frequency. The input clock frequency and clock
multiplication ratio are selectable from a table of popular
SONET, Ethernet, and Fibre Channel rates. In addition
to providing clock multiplication in SONET and datacom
applications, the Si5323 supports SONET-to-datacom
frequency translations. Silicon Laboratories offers a PC-
based software utility, DSPLLsim, that can be used to
look up valid Si5323 frequency translations. This utility
can be downloaded from www.silabs.com/timing. This
information is also available in the Any-Rate Precision
Clock Family Reference Manual, also available from
www.silabs.com/timing.
The Si5323 is based on Silicon Laboratories' 3rd-
generation DSPLL^® technology, which provides any-
rate frequency synthesis and jitter attenuation in a
highly integrated PLL solution that eliminates the need
for external VCXO and loop filter components. The
Si5323 PLL loop bandwidth is selectable via the
BWSEL[1:0] pins and supports a range from 60 Hz to
8.4 kHz. The DSPLLsim software utility can be used to
calculate valid loop bandwidth settings for a given input
clock frequency/clock multiplication ratio.
The Si5323 supports hitless switching between the two
input clocks in compliance with GR-253-CORE and GR-
1244-CORE that greatly minimizes the propagation of
phase transients to the clock outputs during an input
clock transition (<200 ps typ). Manual and automatic
revertive and non-revertive input clock switching options
are available via the AUTOSEL input pin. The Si5323
monitors both input clocks for loss-of-signal and
provides a LOS alarm when it detects missing pulses on
either input clock. The device monitors the lock status of
the PLL. The lock detect algorithm works by
continuously monitoring the phase of the input clock in
relation to the phase of the feedback clock.
The Si5323 provides a digital hold capability that allows
the device to continue generation of a stable output
clock when the selected input reference is lost. During
digital hold, the DSPLL generates an output frequency
based on a historical average that existed a fixed
amount of time before the error event occurred,
eliminating the effects of phase and frequency
transients that may occur immediately preceding digital
hold.
The Si5323 has two differential clock outputs. The
electrical format of the clock outputs is programmable to
support LVPECL, LVDS, CML, or CMOS loads. If not
required, the second clock output can be powered down
to minimize power consumption. The phase difference
between the selected input clock and the output clocks
is adjustable in 200 ps increments for system skew
control. For system-level debugging, a bypass mode is
available which drives the output clock directly from the
input clock, bypassing the internal DSPLL. The device is
powered by a single 1.8, 2.5, or 3.3 V supply.
1.1. External Reference
An external, 38.88 MHz clock or a low-cost
114.285 MHz 3rd overtone crystal is used as part of a
fixed-frequency oscillator within the DSPLL. This
external reference is required for the device to perform
jitter attenuation. Silicon Laboratories recommends
using a high-quality crystal from TXC (www.txc.com.tw),
part number 7MA1400014. An external 38.88 MHz
clock from a high quality OCXO or TCXO can also be
used as a reference for the device.
In digital hold, the DSPLL remains locked to this
external reference. Any changes in the frequency of this
reference when the DSPLL is in digital hold will be
tracked by the output of the device. Note that crystals
can have temperature sensitivities.
1.2. Further Documentation
Consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual (FRM) for more
detailed information about the Si5323. The FRM can be
downloaded from www.silabs.com/timing.
Silicon Laboratories has developed a PC-based
software utility called DSPLLsim to simplify device
configuration, including frequency planning and loop
bandwidth selection. This utility can be downloaded
from www.silabs.com/timing.
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