SI5310 Datasheet, PDF (9/26 Pages) Silicon Laboratories – PRECISION CLOCK MULTIPLIER/REGENERATOR IC

Si5310
Table 4. AC Characteristics (PLL Performance Characteristics) (Continued)
(V_DD = 2.5 V ±5%, T_A = –40 to 85 °C)
Parameter
Symbol Test Condition
Min Typ Max Unit
Jitter Transfer Bandwidth
(MULTSEL = 1,
MULTOUT = 150 to 167 MHz)*
J_BW
Clock Input (MHz) =
—
19
26
kHz
9.375 to 10.438
Clock Input (MHz) = —
38
53
kHz
18.750 to 20.875
Clock Input (MHz) = —
37.500 to 41.750
75
105
kHz
Clock Input (MHz) = —
75.000 to 83.500
150
210
kHz
Clock Input (MHz) = —
150.000 to 167.000
300
420
kHz
Jitter Transfer Peaking
(MULTSEL = 0,
MULTOUT = 600 to 668 MHz)*
J_P
Clock Input (MHz) = —
0.12 0.4
dB
37.500 to 41.750
Clock Input (MHz) = —
0.06
0.2
dB
75.000 to 83.500
Clock Input (MHz) = —
0.03
0.1
dB
150.000 to 167.000
Clock Input (MHz) = —
300.000 to 334.000
0.02 0.066 dB
Clock Input (MHz) = —
600.000 to 668.000
0.01 0.033 dB
Jitter Transfer Peaking
(MULTSEL = 1,
MULTOUT = 150 to 167 MHz)*
J_P
Clock Input (MHz) = —
0.12 0.4
dB
9.375 to 10.438
Clock Input (MHz) = —
0.06
0.2
dB
18.750 to 20.875
Clock Input (MHz) = —
0.03
0.1
dB
37.500 to 41.750
Clock Input (MHz) = —
75.000 to 83.500
0.02 0.066 dB
Clock Input (MHz) = —
150.000 to 167.000
0.01 0.033 dB
Acquisition Time
T_AQ
After falling edge of 1.45
1.5
1.7
ms
PWRDN/CAL
From the return of valid 40
60
150
µs
CLKIN
Frequency Difference at which PLL goes LOL
out of Lock (REFCLK compared to the
divided down VCO clock)
450 600 750 ppm
Frequency Difference at which PLL goes
into Lock (REFCLK compared to the
divided down VCO clock)
LOCK
150 300 450 ppm
*Note: See PLL Performance section of this document for test descriptions.
Rev. 1.2
9