SI5310 Datasheet, PDF (16/26 Pages) Silicon Laboratories – PRECISION CLOCK MULTIPLIER/REGENERATOR IC

Si5310
4.11. Bias Generation Circuitry
The Si5310 makes use of an external resistor to set
internal bias currents. The external resistor allows
precise generation of bias currents which significantly
reduces power consumption compared with traditional
implementations that use an internal resistor. The bias
generation circuitry requires a 10 kΩ (1%) resistor
connected between REXT and GND.
coupling is possible, the 0.1 µF capacitors may be
omitted. The CLKIN and REFCLK input amplifiers
require input signals with minimum differential peak-to-
peak voltages as specified in Table 2 on page 6.
0
CLKIN=155MHz
−1
−2
0
−3
CLKIN=622MHz
−4
−1
CLKIN=9.7MHz
−2
−5
−3
−6
−4
−7
CLKIN=39MHz
−5
−8
−6
−7
−8
−9
10³
10⁴
10⁵
10⁶
Figure 4. PLL Jitter Transfer Functions,
MULTSEL = 0 (MULTOUT = 600–668 MHz)
4.12. Differential Input Circuitry
The Si5310 provides differential inputs for both the input
clock (CLKIN) and the reference clock (REFCLK)
inputs. An example termination for these inputs is
shown in Figure 6. In applications where direct dc
−9
10³
10⁴
10⁵
10⁶
Figure 5. PLL Jitter Transfer Functions,
MULTSEL = 1 (MULTOUT = 150–167 MHz)
4.13. Differential Output Circuitry
The Si5310 utilizes a current mode logic (CML)
architecture to output both the regenerated clock
(CLKOUT) and the multiplied clock (MULTOUT). An
example of output termination with ac coupling is shown
in Figure 10. For applications in which direct dc coupling
is possible, the 0.1 µF capacitors may be omitted. The
differential peak-to-peak voltage swing of the CML is
listed in Table 2 on page 6.
16
Rev. 1.2