SI5310 Datasheet, PDF (20/26 Pages) Silicon Laboratories – PRECISION CLOCK MULTIPLIER/REGENERATOR IC

Si5310
Pin #
12, 13
15
16, 17
19
20
Table 11. Si5310 Pin Descriptions (Continued)
Pin Name
I/O Signal Level
Description
CLKOUT–,
O
CLKOUT+
PWRDN/CAL
I
CML
LVTTL
Differential Clock Output.
The clock output signal is a regenerated version of
the input clock signal present on CLKIN. It is phase
aligned with MULTOUT and is updated on the rising
edge of MULTOUT.
Note: Connection of an improperly terminated
transmission line to the CLKOUT output can cause
reflections that may adversely affect the
performance of the MULTOUT output. If the
CLKOUT output is not used, these pins should be
either tied to V_DD (recommended), left
unconnected, or connected to a properly
terminated transmission line.
Power Down.
To shut down the high-speed outputs and reduce
power consumption, hold this pin high. For normal
operation, hold this pin low.
Calibration.
MULTOUT–,
O
MULTOUT+
MULTSEL
I
CML
LVTTL
To initiate an internal self-calibration, force a high-to-
low transition on this pin. (See "4.9. PLL Self-Cali-
bration" on page 15.)
Note: This input has a weak internal pulldown.
Differential Multiplier Output.
The multiplier output is generated from the signal
present on CLKIN. In the absence of CLKIN, the
REFCLK is used to bound the frequency of MUL-
TOUT according to Table 4 on page 8.
Note: Connection of an improperly terminated
transmission line to the MULTOUT output can
cause reflections that may adversely affect the
CLKOUT output. If the MULTOUT output is not
used, these pins should be either tied to V_DD
(recommended), left unconnected, or connected to
a properly terminated transmission line.
Multiplier Rate Select.
This pin configures the onboard PLL-based clock
multiplier for clock generation at one of two user
selectable clock rates.
Note: This input has a weak internal pulldown.
NC
No Connect.
20
Rev. 1.2