SI5017 Datasheet, PDF (9/26 Pages) Silicon Laboratories – OC-48/STM-16 SONET/SDH CDR IC WITH LIMITING AMPLIFIER

Si5017
Table 4. AC Characteristics (PLL Characteristics)
(V_DD =3.3 V ±5%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
Jitter Tolerance
(OC-48)*
J_TOL(PP)
f = 600 Hz
40
f = 6000 Hz
4
f = 100 kHz
3
f = 1 MHz
0.3
RMS Jitter Generation^*
J_GEN(rms) with no jitter on serial data —
Peak-to-Peak Jitter Generation^*
J_GEN(PP) with no jitter on serial data
—
Jitter Transfer Bandwidth^*
J_BW
OC-48
—
Jitter Transfer Peaking^*
J_P
—
Acquisition Time
(Reference clock applied)
T_AQ
After falling edge of
—
RESET/CAL
—
—
—
—
3.0
25
—
0.03
1.6
—
UI_PP
—
UI_PP
—
UI_PP
—
UI_PP
5.0 mUI
55
mUI
2.0 MHz
0.1
dB
2.2
ms
From the return of valid
20
100
500
µs
data
Acquisition Time
(Reference-less operation)
T_AQ
After falling edge of
—
2.0
5.5
ms
RESET/CAL
From the return of valid
1.5
2.5
5.5
ms
data
Reference Clock Range
See Table 7 on page 13.
f_CLK / 16
f_CLK / 32
f_CLK / 128
— 155.52 —
—
77.76
—
—
19.44
—
MHz
Input Reference Clock Frequency
Tolerance
C_TOL
–500
—
+500 ppm
Frequency Difference at which
Receive PLL goes out of Lock
(REFCLK compared to the divided
down VCO clock)
—
±650
—
ppm
*Note: As defined in Bellcore specifications: GR-253-CORE, Issue 3, September 2000. Using PRBS 2²³ – 1 data pattern.
9
Rev. 1.4