SI5017 Datasheet, PDF (16/26 Pages) Silicon Laboratories – OC-48/STM-16 SONET/SDH CDR IC WITH LIMITING AMPLIFIER

Si5017
4.17. Differential Input Circuitry
The Si5017 provides differential inputs for both the high-speed data (DIN) and the reference clock (REFCLK)
inputs. An example termination for these inputs is shown in Figures 10 and 11, respectively. In applications where
direct dc coupling is possible, the 0.1 µF capacitors may be omitted. (LOS operation is only guaranteed when ac
coupled.) The data input limiting amplifier requires an input signal with a differential peak-to-peak voltage as
specified in Table 2 on page 7 to ensure a BER of at least 10^–12. The REFCLK input differential peak-to-peak
voltage requirement is also specified in Table 2.
Clock source
0.1 µF
0.1 µF
Zo = 50 Ω
Si5017
2.5 V (±5%)
2.5 kΩ
RFCLK +
100 Ω
Zo = 50 Ω
10 kΩ
RFCLK –
2.5 kΩ
10 kΩ
GND
Figure 10. Input Termination for REFCLK (ac coupled)
TIA
Si5017
2.5 V (±5%)
0.1 µF
Zo = 50 Ω
DIN+
50 Ω
5 kΩ
0.1 µF
Zo = 50 Ω
DIN–
50 Ω
7.5 kΩ
GND
Figure 11. Input Termination for DIN (ac coupled)
16
Rev. 1.4