SI5017 Datasheet, PDF (8/26 Pages) Silicon Laboratories – OC-48/STM-16 SONET/SDH CDR IC WITH LIMITING AMPLIFIER

Si5017
Table 3. AC Characteristics (Clock and Data)
(V_DD = 3.3 V ±5%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Output Clock Rate
f_CLK
Output Clock Rise Time
t_R
Output Clock Fall Time
t_F
Output Clock Duty Cycle
Figure 3
Figure 3
Output Data Rise Time
Output Data Fall Time
Clock to Data Delay
FEC (2.7 Gbps)
OC-48
t_R
t_F
t_Cr-D
Figure 3
Figure 3
Figure 2
Clock to Data Delay
FEC (2.7 Gbps)
OC-48
t_Cf-D
Figure 2
Input Return Loss
100 kHz–1.5 GHz
1.5 GHz–4.0 GHz
Slicing Level Offset
(relative to the internally set input
common mode voltage)
Loss-of-Signal Range^*
(peak-to-peak differential)
V_SLICE
V_LOS
SLICE_LVL = 750 mV to
2.25 V
LOS_LVL = 1.50 to 2.50 V
Loss-of-Signal Response Time
t_LOS
Figure 5
*Note: Adjustment voltage is calculated as follows: V_LOS = (LOS_LVL – 1.50)/25.
Min Typ Max Unit
2.4
—
2.7 GHz
—
70
90
ps
—
70
90
ps
48
50
52 % of
UI
—
80
110
ps
—
80
110
ps
190 230
265
ps
190
230
265
–70 –40
–10
ps
–60 –30
0
–15
—
–10
—
—
dB
—
dB
See Figure 8 on page 14.
0
—
40
mV
8
20
25
µs
8
Rev. 1.4