SI5017 Datasheet, PDF (21/26 Pages) Silicon Laboratories – OC-48/STM-16 SONET/SDH CDR IC WITH LIMITING AMPLIFIER

Pin #
22
23
24
26
27
28
GND Pad
Si5017
Table 8. Si5017 Pin Descriptions (Continued)
Pin Name
CLKOUT–
CLKOUT+
CLKDSBL
BER_LVL
BER_ALM
NC
GND
I/O Signal Level
Description
O
CML
Differential Clock Output.
The output clock is recovered from the data signal
present on DIN except when LTR is asserted or the
LOL state has been entered.
I
LVTTL Clock Disable.
When this input is high, the CLKOUT output drivers
are disabled. For normal operation, this pin should
be low.
Note: This input has a weak internal pulldown.
I
Bit Error Rate Level Control.
The BER threshold level is set by applying a volt-
age to this pin. When the BER exceeds the pro-
grammed threshold, BER_ALM is driven low. If this
pin is tied to GND, BER_ALM is disabled.
O
LVTTL Bit Error Rate Alarm.
This pin will be driven low to indicate that the BER
threshold set by BER_LVL has been exceeded.
There is no hysteresis.
No Connect.
Leave this pin disconnected.
GND
Supply Ground.
Nominally 0.0 V. The GND pad found on the bottom
of the 28-lead QFN (see Figure 16 on page 23)
must be connected directly to supply ground.
Minimize the ground path inductance for optimal
performance.
Rev. 1.4
21