SI5017 Datasheet, PDF (15/26 Pages) Silicon Laboratories – OC-48/STM-16 SONET/SDH CDR IC WITH LIMITING AMPLIFIER

Si5017
4.10. PLL Performance
The PLL implementation used in the Si5017 is fully
compliant with the jitter specifications proposed for
SONET/SDH equipment by Bellcore GR-253-CORE,
Issue 3, September 2000 and ITU-T G.958.
4.10.1. Jitter Tolerance
The Si5017’s tolerance to input jitter exceeds that of the
Bellcore/ITU mask shown in Figure 8. This mask
defines the level of peak-to-peak sinusoid jitter that
must be tolerated when applied to the differential data
input of the device.
4.10.2. Jitter Transfer
The Si5017 exceeds all relevant Bellcore/ITU
specifications related to SONET/SDH jitter transfer.
Jitter transfer is defined as the ratio of output signal jitter
to input signal jitter as a function of jitter frequency.
These measurements are made with an input test signal
that is degraded with sinusoidal jitter whose magnitude
is defined by the mask in Figure 9.
Jitter
Transfer
0.1 dB
Acceptable
Range
20 dB/Decade
Slope
the DSPLL on powerup. Calibration may also be
initiated by a high-to-low transition on the RESET/CAL
pin. The RESET/CAL pin must be held high for at least
1 µs. When RESET/CAL is released (set to low) the
digital logic resets to a known initial condition,
recalibrates the DSPLL, and begins to lock to the
incoming data stream. For a valid reset to occur when
using Reference mode, a proper, external reference
clock frequency must be applied as specified in Table 7.
4.12. Clock Disable
The Si5017 provides a clock disable pin (CLK_DSBL)
that is used to disable the recovered clock output
(CLKOUT). When the CLK_DSBL pin is asserted, the
positive and negative terminals of CLKOUT are tied to
VDD through 100 Ω on-chip resistors.
4.13. Data Squelch
The Si5017 provides a data squelching pin (DSQLCH)
that is used to set the recovered data output (DOUT) to
binary zero. When the DSQLCH pin is asserted, the
DOUT+ signal is held low and the DOUT– signal is held
high. This pin can be is used to squelch corrupt data
during LOS and LOL situations. Care must be taken
when ac coupling these outputs; a long string of zeros
or ones will not be held through ac coupling capacitors.
4.14. Device Grounding
The Si5017 uses the GND pad on the bottom of the 28-
pin micro leaded package (QFN) for device ground. This
pad should be connected directly to the analog supply
ground. See Figure 15 on page 19 and Figure 16 on
page 23 for the ground (GND) pad location.
Fc
Frequency
SONET
Data Rate
OC-48
Fc
(kHz)
2000
Figure 9. Jitter Transfer Specification
4.10.3. Jitter Generation
The Si5017 exceeds all relevant specifications for jitter
generation proposed for SONET/SDH equipment. The
jitter generation specification defines the amount of jitter
that may be present on the recovered clock and data
outputs when a jitter free input signal is provided. The
Si5017 typically generates less than 3.0 mUI_rms of jitter
when presented with jitter-free input data.
4.11. RESET/DSPLL Calibration
4.15. Bias Generation Circuitry
The Si5017 makes use of an external resistor to set
internal bias currents. The external resistor allows
precise generation of bias currents which significantly
reduces power consumption versus traditional
implementations that use an internal resistor. The bias
generation circuitry requires a 10 kΩ (1%) resistor
connected between REXT and GND.
4.16. Voltage Regulator
The Si5017 operates from a 3.3 V external supply
voltage. Internally the device operates from a 2.5 V
supply. The Si5017 regulates 2.5 V internally down from
the external 3.3 V supply.
In addition to supporting 3.3 V systems, the on-chip
linear regulator offers better power supply noise
rejection versus a direct 2.5 V supply.
The Si5017 achieves optimal jitter performance by
automatically calibrating the loop gain parameters within
15
Rev. 1.4