SI5017 Datasheet, PDF (24/26 Pages) Silicon Laboratories – OC-48/STM-16 SONET/SDH CDR IC WITH LIMITING AMPLIFIER

Si5017
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 1.0
Added Figure 4, “PLL Acquisition Time,” on page 6.
Table 2 on page 7
Added FEC (2.7 GHz) Supply Current
Updated values: Supply Current
Added FEC (2.7 GHz) Power Dissipation
Updated values: Power Dissipation
Updated values: Common Mode Input Voltage
(REFCLK)
Updated values: Output Common Mode Voltage
Table 3 on page 8
Added separate Output Clock Rise Time
Added separate Output Clock Fall Time
Updated values: Output Clock Rise Time
Updated values: Output Clock Fall Time
Table 4 on page 9
Updated values: Jitter Tolerance (OC-48) for f = 1 MHz
Updated values: Acquisition Time
(reference clock applied)
Updated values: Acquisition Time
(reference-less operation)
Updated values: Freq Difference at which Receive PLL
goes out of Lock
Updated values: Freq Difference at which Receive PLL
goes into Lock
Removed “Hysteresis Dependency” Figure.
Added Figure 7, “LOS Signal Hysteresis,” on page
13.
Corrected error: Table 8 on page 19—changed
description for LOS_LVL from “LOS is disabled when
the voltage applied is less than 500 mV” to “LOS is
disabled when the voltage applied is less than
1.0 V.”
Revision 1.0 to Revision 1.1
Corrected “Revision 0.1 to Revision 1.0” Change
List.
Updated Figure 16, “28-Lead Quad Flat No-Lead
(QFN),” on page 23.
Updated Table 9, “Package Diagram Dimensions,”
on page 23.
Changed dimension A.
Changed dimension E2.
Revision 1.2 to Revision 1.3
Table 2 on page 7.
Updated power consumption.
Updated R_IN.
Table 3 on page 8.
Updated clock to data delay.
Updated slicing level accuracy.
Table 4 on page 9.
Updated tolerance.
Updated acquisition time.
Updated reference clock information.
Updated "Ordering Guide" on page 22.
Added “X” to part number.
Revision 1.3 to Revision 1.4
Updated Table 2 on page 7.
Added limits for V_ICM.
Updated V_OD.
Updated Table 3 on page 8.
Updated T_Cr-D.
Updated T_Cf-D.
Revised SLICE specification.
Updated Table 4 on page 9.
T_AQ min/max values updated.
Updated "Loss-of-Signal (LOS)" on page 13.
Added note describing valid signal.
Updated Figure 6, “LOS_LVL Mapping,” on page 13.
Updated "Data Slicing Level" on page 14.
Added Figure 8 on page 14.
Revised text.
Revision 1.1 to Revision 1.2
Added Figure 5, “LOS Response Time,” on page 6.
Updated Table 2 on page 7
Added “Output Common Mode Voltage (DOUT)” with
updated values.
Added “Output Common Mode Voltage (CLKOUT)” with
updated values.
Table 3 on page 8.
Added “Output Clock Duty Cycle”
Added “Loss-of-Signal Response Time”
Updated Table 8 on page 19
Changed “clock input” to “DIN inputs” for Loss-of-Signal.
24
Rev. 1.4