SI5017 Datasheet, PDF (19/26 Pages) Silicon Laboratories – OC-48/STM-16 SONET/SDH CDR IC WITH LIMITING AMPLIFIER

5. Pin Descriptions: Si5017
Si5017
28 27 26 25 24 23 22
VDD 1
21 VDD
VDD 2
20 REXT
LOS_LVL 3
SLICE_LVL 4
REFCLK+ 5
GND
Pad
19 RESET/CAL
18 VDD
17 DOUT+
REFCLK– 6
16 DOUT–
LOL 7
15 TDI
8 9 10 11 12 13 14
Pin #
1,2,11,14,18,
21,25
3
4
5
6
Pin Name
VDD
LOS_LVL
SLICE_LVL
REFCLK+
REFCLK–
Figure 15. Si5017 Pin Configuration
Table 8. Si5017 Pin Descriptions
I/O Signal Level
Description
3.3 V
Supply Voltage.
Nominally 3.3 V.
I
LOS Level Control.
The LOS threshold is set by the input voltage level
applied to this pin. Figure 6 on page 13 shows the
input setting to output threshold mapping.
LOS is disabled when the voltage applied is less
than 1 V.
I
Slicing Level Control.
The slicing threshold level is set by applying a volt-
age to this pin as described in the Slicing Level sec-
tion of the data sheet. If this pin is tied to GND,
slicing level adjustment is disabled, and the slicing
level is set to the midpoint of the differential input
signal on DIN. Slicing level becomes active when
the voltage applied to the pin is greater than
500 mV.
I
See Table 2 Differential Reference Clock (Optional).
When present, the reference clock sets the center
operating frequency of the DSPLL for clock and
data recovery. Tie REFCLK+ to VDD and REFCLK–
to GND to operate without an external reference
clock.
See Table 7 on page 13 for typical reference clock
frequencies.
Rev. 1.4
19