EFM8UB1 Datasheet, PDF (9/59 Pages) Silicon Laboratories – The EFM8UB1 highlighted features are listed below

EFM8UB1 Data Sheet
System Overview
System Management Bus / I2C (SMB0)
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specifica-
tion, version 1.1, and compatible with the I²C serial bus.
The SMBus module includes the following features:
• Standard (up to 100 kbps) and Fast (400 kbps) transfer speeds
• Support for master, slave, and multi-master modes
• Hardware synchronization and arbitration for multi-master mode
• Clock low extending (clock stretching) to interface with faster masters
• Hardware support for 7-bit slave and general call address recognition
• Firmware support for 10-bit slave address decoding
• Ability to inhibit all slave states
• Programmable data setup/hold times
• Transmit and receive buffers to help increase throughput in faster applications
I2C Slave (I2CSLAVE0)
The I2C Slave interface is a 2-wire, bidirectional serial bus that is compatible with the I2C Bus Specification 3.0. It is capable of transfer-
ring in high-speed mode (HS-mode) at speeds of up to 3.4 Mbps. Firmware can write to the I2C interface, and the I2C interface can
autonomously control the serial transfer of data. The interface also supports clock stretching for cases where the core may be tempora-
rily prohibited from transmitting a byte or processing a received byte during an I2C transaction. This module operates only as an I2C
slave device.
The I2C module includes the following features:
• Standard (up to 100 kbps), Fast (400 kbps), Fast Plus (1 Mbps), and High-speed (3.4 Mbps) transfer speeds
• Support for slave mode only
• Clock low extending (clock stretching) to interface with faster masters
• Hardware support for 7-bit slave address recognition
16-bit CRC (CRC0)
The cyclic redundancy check (CRC) module performs a CRC using a 16-bit polynomial. CRC0 accepts a stream of 8-bit data and posts
the 16-bit result to an internal register. In addition to using the CRC block for data manipulation, hardware can automatically CRC the
flash contents of the device.
The CRC module is designed to provide hardware calculations for flash memory verification and communications protocols. The CRC
module supports the standard CCITT-16 16-bit polynomial (0x1021), and includes the following features:
• Support for CCITT-16 polynomial
• Byte-level bit reversal
• Automatic CRC of flash contents on one or more 256-byte blocks
• Initial seed selection of 0x0000 or 0xFFFF
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