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EFM8UB1 Datasheet, PDF (8/59 Pages) Silicon Laboratories – The EFM8UB1 highlighted features are listed below | |||
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EFM8UB1 Data Sheet
System Overview
Universal Asynchronous Receiver/Transmitter (UART0)
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support
allows a wide range of clock sources to generate standard baud rates. Received data buffering allows UART0 to start reception of a
second incoming data byte before software has finished reading the previous data byte.
The UART module provides the following features:
⢠Asynchronous transmissions and receptions
⢠Baud rates up to SYSCLK/2 (transmit) or SYSCLK/8 (receive)
⢠8- or 9-bit data
⢠Automatic start and stop generation
⢠Single-byte buffer on transmit and receive
Universal Asynchronous Receiver/Transmitter (UART1)
UART1 is an asynchronous, full duplex serial port offering a variety of data formatting options. A dedicated baud rate generator with a
16-bit timer and selectable prescaler is included, which can generate a wide range of baud rates. A received data FIFO allows UART1
to receive multiple bytes before data is lost and an overflow occurs.
UART1 provides the following features:
⢠Asynchronous transmissions and receptions.
⢠Dedicated baud rate generator supports baud rates up to SYSCLK/2 (transmit) or SYSCLK/8 (receive).
⢠5, 6, 7, 8, or 9 bit data.
⢠Automatic start and stop generation.
⢠Automatic parity generation and checking.
⢠Four byte FIFO on transmit and receive.
⢠Auto-baud detection.
⢠LIN break and sync field detection.
⢠CTS / RTS hardware flow control.
Serial Peripheral Interface (SPI0)
The serial peripheral interface (SPI) module provides access to a flexible, full-duplex synchronous serial bus. The SPI can operate as a
master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select
(NSS) signal can be configured as an input to select the SPI in slave mode, or to disable master mode operation in a multi-master
environment, avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be
configured as a firmware-controlled chip-select output in master mode, or disabled to reduce the number of pins required. Additional
general purpose port I/O pins can be used to select multiple slave devices in master mode.
⢠Supports 3- or 4-wire master or slave modes.
⢠Supports external clock frequencies up to 12 Mbps in master or slave mode.
⢠Support for all clock phase and polarity modes.
⢠8-bit programmable clock rate (master).
⢠Programmable receive timeout (slave).
⢠Four byte FIFO on transmit and receive.
⢠Can operate in suspend or snooze modes and wake the CPU on reception of a byte.
⢠Support for multiple masters on the same data lines.
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