EFM8UB1 Datasheet, PDF (4/59 Pages) Silicon Laboratories – The EFM8UB1 highlighted features are listed below

3. System Overview
3.1 Introduction
EFM8UB1 Data Sheet
System Overview
C2CK/RSTb
C2D
Debug /
Programming
Hardware
Reset
Power-On
Reset
CIP-51 8051 Controller
Core
16 KB ISP Flash
Program Memory
256 Byte SRAM
Supply
Monitor
2048 Byte XRAM
VDD
VREGIN
GND
D+
D-
VBUS
Independent
Watchdog
Timer
EXTCLK
Power
Net
Voltage
Regulators
System Clock
Configuration
Low Freq.
Oscillator
CMOS Oscillator
Input
48 MHz 1.5%
Oscillator
SYSCLK
SFR
Bus
Clock
Recovery
24.5 MHz 2%
Oscillator
USB Peripheral
Full / Low
Speed
Transceiver
Controller
Charge
Detection
1 KB RAM
Low Power
Port I/O Configuration
Digital Peripherals
UART0
UART1
Timers 0,
1, 2, 3, 4
3-ch PCA
I2C Slave
I2C /
SMBus
SPI
CRC
Priority
Crossbar
Decoder
Crossbar Control
Analog Peripherals
Internal
Reference
VDD
VREF
12/10 bit
ADC
VDD
Temp
Sensor
+-+-
2 Comparators
Figure 3.1. Detailed EFM8UB1 Block Diagram
Port 0
Drivers
Port 1
Drivers
Port 2
Drivers
Port 3
Drivers
P0.n
P1.n
P2.n
P3.n
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