EFM8UB1 Datasheet, PDF (16/59 Pages) Silicon Laboratories – The EFM8UB1 highlighted features are listed below

EFM8UB1 Data Sheet
Electrical Specifications
Parameter
Symbol Test Condition
Min
Typ
Max
Unit
5V Regulator
I_VREG
Normal Mode
(SUSEN = 0, BIASENB = 0)
—
245
340
μA
Suspend Mode
—
60
100
μA
(SUSEN = 1, BIASENB = 0)
Bias Disabled
—
2.5
10
μA
(BIASENB = 1)
Disabled
—
2.5
—
nA
(BIASENB = 1, REG1ENB = 1)
USB (USB0) Full-Speed
I_USB
Low Energy Mode, 64 byte 1ms IN
—
850
—
μA
Interrupt transfers
Low Energy Mode, 64 byte 1ms
—
250
—
μA
OUT Interrupt transfers
Low Energy Mode, Idle (SOF only)
—
50
—
μA
Note:
1. Currents are additive. For example, where I_DD is specified and the mode is not mutually exclusive, enabling the functions increa-
ses supply current by the specified amount.
2. Includes supply current from internal LDO regulator, supply monitor, and High Frequency Oscillator.
3. Includes supply current from internal LDO regulator, supply monitor, and Low Frequency Oscillator.
4. ADC0 always-on power excludes internal reference supply current.
5. The internal reference is enabled as-needed when operating the ADC in burst mode to save power.
4.1.3 Reset and Supply Monitor
Table 4.3. Reset and Supply Monitor
Parameter
Symbol
VDD Supply Monitor Threshold
V_VDDM
Power-On Reset (POR) Threshold V_POR
VDD Ramp Time
t_RMP
Reset Delay from POR
t_POR
Reset Delay from non-POR source t_RST
RST Low Time to Generate Reset t_RSTL
Missing Clock Detector Response t_MCD
Time (final rising edge to reset)
Missing Clock Detector Trigger
Frequency
F_MCD
VDD Supply Monitor Turn-On Time t_MON
Test Condition
Rising Voltage on VDD
Falling Voltage on VDD
Time to V_DD > 2.2 V
Relative to V_DD > V_POR
Time between release of reset
source and code execution
F_SYSCLK >1 MHz
Min
Typ
Max
Unit
1.95
2.05
2.15
V
—
1.2
—
V
0.75
—
1.36
V
10
—
—
μs
3
10
31
ms
—
50
—
μs
15
—
—
μs
—
0.625
1.2
ms
—
7.5
13.5
kHz
—
2
—
μs
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