EFM8UB1 Datasheet, PDF (7/59 Pages) Silicon Laboratories – The EFM8UB1 highlighted features are listed below

EFM8UB1 Data Sheet
System Overview
Timers (Timer 0, Timer 1, Timer 2, Timer 3, and Timer 4)
Several counter/timers are included in the device: two are 16-bit counter/timers compatible with those found in the standard 8051, and
the rest are 16-bit auto-reload timers for timing peripherals or for general purpose use. These timers can be used to measure time inter-
vals, count external events and generate periodic interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary
modes of operation. The other timers offer both 16-bit and split 8-bit timer functionality with auto-reload and capture capabilities.
Timer 0 and Timer 1 include the following features:
• Standard 8051 timers, supporting backwards-compatibility with firmware and hardware.
• Clock sources include SYSCLK, SYSCLK divided by 12, 4, or 48, the External Clock divided by 8, or an external pin.
• 8-bit auto-reload counter/timer mode
• 13-bit counter/timer mode
• 16-bit counter/timer mode
• Dual 8-bit counter/timer mode (Timer 0)
Timer 2, Timer 3 and Timer 4 are 16-bit timers including the following features:
• Clock sources for all timers include SYSCLK, SYSCLK divided by 12, or the External Clock divided by 8.
• LFOSC0 divided by 8 may be used to clock Timer 3 and Timer 4 in active or suspend/snooze power modes.
• Timer 4 is a low-power wake source, and can be chained together with Timer 3.
• 16-bit auto-reload timer mode.
• Dual 8-bit auto-reload timer mode.
• External pin capture.
• LFOSC0 capture.
• Comparator 0 capture.
• USB Start-of-Frame (SOF) capture.
Watchdog Timer (WDT0)
The device includes a programmable watchdog timer (WDT) running off the low-frequency oscillator. A WDT overflow forces the MCU
into the reset state. To prevent the reset, the WDT must be restarted by application software before overflow. If the system experiences
a software or hardware malfunction preventing the software from restarting the WDT, the WDT overflows and causes a reset. Following
a reset, the WDT is automatically enabled and running with the default maximum time interval. If needed, the WDT can be disabled by
system software or locked on to prevent accidental disabling. Once locked, the WDT cannot be disabled until the next system reset.
The state of the RST pin is unaffected by this reset.
The Watchdog Timer has the following features:
• Programmable timeout interval
• Runs from the low-frequency oscillator
• Lock-out feature to prevent any modification until a system reset
3.6 Communications and Other Digital Peripherals
Universal Serial Bus (USB0)
The USB0 peripheral provides a full-speed USB 2.0 compliant device controller and PHY with additional Low Energy USB features. The
device supports both full-speed (12MBit/s) and low speed (1.5MBit/s) operation, and includes a dedicated USB oscillator with clock re-
covery mechanism for crystal-free operation. No external components are required. The USB function controller (USB0) consists of a
Serial Interface Engine (SIE), USB transceiver (including matching resistors and configurable pull-up resistors), and 1 KB FIFO block.
The Low Energy Mode ensures the current consumption is optimized and enables USB communication on a strict power budget.
The USB0 module includes the following features:
• Full and Low Speed functionality.
• Implements 4 bidirectional endpoints.
• Low Energy Mode to reduce active supply current based on bus bandwidth.
• USB 2.0 compliant USB peripheral support (no host capability).
• Direct module access to 1 KB of RAM for FIFO memory.
• Clock recovery to meet USB clocking requirements with no external components.
• Charger detection circuitry with automatic detection of SDP, CDP, and DCP interfaces.
• D+ and D- can be routed to ADC input to support ACM and proprietary charger architectures.
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