EFM8UB1 Datasheet, PDF (30/59 Pages) Silicon Laboratories – The EFM8UB1 highlighted features are listed below

5. Typical Connection Diagrams
EFM8UB1 Data Sheet
Typical Connection Diagrams
5.1 Power
The figure below shows a typical connection diagram for the power pins of the EFM8UB1 devices when the internal regulator used and
USB is connected (bus-powered). VBUS is not used as a sense pin in this scenario, so that pin can be used as a standard GPIO.
USB 5 V (in)
4.7 µF and 0.1 µF bypass
capacitors required for
each power pin placed as
close to the pins as
possible.
EFM8UB1 Device
3.3 V (out)
VREGIN
VDD
Voltage
Regulator
GND
Figure 5.1. Connection Diagram with Voltage Regulator Used and USB Connected (Bus-Powered)
The figure below shows a typical connection diagram for the power pins of the EFM8UB1 devices when the internal regulator used and
USB is connected (self-powered). The VBUS signal is used to detect when USB is connected to a host device.
4.7 µF and 0.1 µF bypass
capacitors required for
each power pin placed as
close to the pins as
possible.
3.6-5.25 V (in)
USB 5 V
(sense)
P3.1 / VBUS
3.3 V (out)
VREGIN
VDD
EFM8UB1 Device
Voltage
Regulator
GND
Figure 5.2. Connection Diagram with Voltage Regulator Used and USB Connected (Self-Powered)
The figure below shows a typical connection diagram for the power pins of the EFM8UB1 devices when the internal 5 V-to-3.3 V regula-
tor is not used.
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.1 | 29