SI53112 Datasheet, PDF (8/35 Pages) Silicon Laboratories – DB1200ZL 12-OUTPUT PCIE GEN 3 BUFFER

Si53112
Table 5. DIF 0.7 V AC Timing Characteristics (Non-Spread Spectrum Mode)¹
Parameter
Symbol
CLK 100 MHz, 133 MHz
Min
Typ
Max
Clock Stabilization Time
T_STAB
Long Term Accuracy
L_ACC
Absolute Host CLK Period (100MHz) T_ABS
Absolute Host CLK Period (133MHz) T_ABS
Edge Rate
Edge_rate
—
—
9.94900
7.44925
1.0
1.5
1.8
100
10.05100
7.55075
4.0
Rise Time Variation
∆ Trise
—
125
Fall Time Variation
∆ Tfall
—
125
Rise/Fall Matching
Voltage High (typ 0.7 V)
Voltage Low (typ 0.7 V)
Maximum Voltage
Absolute Crossing Point Voltages
T_{RISE_MAT}/
T_{FALL_MAT}
V_HIGH
V_LOW
V_MAX
Vox_ABS
—
660
–150
—
250
20
850
150
1150
550
Unit
ms
ppm
ns
ns
V/ns
ps
ps
%
mV
mV
mV
mV
Relative Crossing Point Voltages
Vox_REL
Total Variation of Vcross Over All
Total ∆
—
Edges
Vox
Duty Cycle
DC
45
Maximum Voltage (Overshoot)
Maximum Voltage (Undershoot)
V_ovs
—
V_uds
—
140
mV
55
%
V_High + 0.3
V
V_Low – 0.3
V
Notes
2
3_,4_,5
3_,4_,6
3_,4_,6
3_,4_,7
3_,8_,9
3_,8_,9
3_,8_,10_,11
3_,8_,12
3_,8_,13
8
3_,8_,14_,15_,
16
3_,8_,16_,17
3_,8_,18
3_,4
3_,8_,19
3_,8_,20
8
Rev. 1.1