SI53112 Datasheet, PDF (31/35 Pages) Silicon Laboratories – DB1200ZL 12-OUTPUT PCIE GEN 3 BUFFER

Si53112
8. Package Outline
Figure 13 illustrates the package details for the Si53112. Table 26 lists the values for the dimensions shown in the
illustration.
Figure 13. 64-Pin Quad Flat No Lead (QFN) Package
Table 26. Package Diagram Dimensions
Dimension
Min
A
0.80
Nom
Max
0.85
0.90
A1
0.00
0.02
0.05
b
0.18
0.25
0.30
D
9.00 BSC.
D2
6.00
6.10
6.20
e
0.50 BSC.
E
9.00 BSC.
E2
6.00
6.10
6.20
L
0.30
0.40
0.50
aaa
0.10
bbb
0.10
ccc
0.08
ddd
0.10
eee
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
Rev. 1.1
31