SI53112 Datasheet, PDF (21/35 Pages) Silicon Laboratories – DB1200ZL 12-OUTPUT PCIE GEN 3 BUFFER

Si53112
Table 18. Byte 1: Output Enable Control Register
Bit
Description
If Bit = 0 If Bit = 1
Type
Default Output(s)
Affected
0
Output Enable DIF 0 Low/Low for Enabled
RW
Si53112
1
DIF[0]
1
Output Enable DIF 1 Low/Low for Enabled
RW
Si53112
1
DIF[1]
2
Output Enable DIF 2 Low/Low for Enabled
RW
Si53112
1
DIF[2]
3
Output Enable DIF 3 Low/Low for Enabled
RW
Si53112
1
DIF[3]
4
Output Enable DIF 4 Low/Low for Enabled
RW
Si53112
1
DIF[4]
5
Output Enable DIF 5 Low/Low for Enabled
RW
Si53112
1
DIF[5]
6
Output Enable DIF 6 Low/Low for Enabled
RW
Si53112
1
DIF[6]
7
Output Enable DIF 7 Low/Low for Enabled
RW
Si53112
1
DIF[7]
Rev. 1.1
21