SI53112 Datasheet, PDF (20/35 Pages) Silicon Laboratories – DB1200ZL 12-OUTPUT PCIE GEN 3 BUFFER

Si53112
4.3. Control Registers
Table 17. Byte 0: Frequency Select, Output Enable, PLL Mode Control Register
Bit
Description
If Bit = 0 If Bit = 1 Type
Default
Output(s)
Affected
0
100M_133M#
133 MHz 100 MHz
R
Latched at DIF[11:0]
Frequency Select
power up
1
PLL Mode 0
See PLL Operating Mode RW
1
2
PLL Mode 1
Readback Table
RW
1
3 PLL Software Enable HW Latch SMBUS
RW
0
Control
4
Reserved
0
5
Reserved
0
6
PLL Mode 0
See PLL Operating Mode
R
Latched at
Readback Table
power up
7
PLL Mode 1
See PLL Operating Mode
R
Latched at
Readback Table
power up
Note: Byte 0, bit_[3:1] are BW PLL SW enable for the DB1200ZL. Setting bit 3 to 1 allows the user to override the Latch value
from pin 5 via use of bits 2 and 1. Use the values from the PLL Operating Mode Readback Table. Note that Bits 7 and 6
will keep the value originally latched on pin 5. A warm reset of the system will have to be accomplished if the user
changes these bits.
20
Rev. 1.1