SI53112 Datasheet, PDF (10/35 Pages) Silicon Laboratories – DB1200ZL 12-OUTPUT PCIE GEN 3 BUFFER

Si53112
Table 6. Clock Periods Differential Clock Outputs with SSC Disabled
SSC ON
Measurement Window
Center
Freq, MHz ^{1 Clock}
1 µs
0.1 s
0.1 s
0.1 s
1 µs
-C-C Jitter
AbsPer
Min
-SSC
Short
Term AVG
Min
-ppm
Long
Term AVG
Min
0 ppm
Period
Nominal
+ppm
Long
Term AVG
Max
+SSC
Short
Term AVG
Max
1 Clock
+C-C
Jitter
AbsPer
Max
100.00 9.94900
9.99900 10.00000 10.00100
10.05100
133.33 7.44925
7.49925 7.50000 7.50075
7.55075
Units
ns
ns
Table 7. Clock Periods Differential Clock Outputs with SSC Enabled
SSC ON
Measurement Window
Center
Freq, MHz ^{1 Clock}
1 µs
0.1 s
0.1 s
0.1 s
1 µs
-C-C Jitter
AbsPer
Min
-SSC
Short
Term AVG
Min
-ppm
Long
Term AVG
Min
0 ppm
Period
Nominal
+ppm
Long
Term AVG
Max
+SSC
Short
Term AVG
Max
1 Clock
+C-C
Jitter
AbsPer
Max
99.75
9.94900 9.99900 10.02406 10.02506 10.02607 10.05126 10.10126
133.33 7.44925 7.49925 7.51805 7.51880 7.51955 7.53845 7.58845
Units
ns
ns
Table 8. Absolute Maximum Ratings
Parameter
Symbol
Min
Max
3.3 V Core Supply Voltage¹
VDD/VDD_A
—
4.6
3.3 V I/O Supply Voltage¹
VDD_IO
—
4.6
3.3 V Input High Voltage^1,2
VIH
—
4.6
3.3 V Input Low Voltage¹
VIL
−0.5
—
Storage Temperature¹
Input ESD protection³
t_s
–65
150
ESD
2000
—
Notes:
1. Consult manufacturer regarding extended operation in excess of normal dc operating parameters.
2. Maximum VIH is not to exceed maximum V_DD.
3. Human body model.
Unit
V
V
V
V
°C
V
10
Rev. 1.1