SI53112 Datasheet, PDF (4/35 Pages) Silicon Laboratories – DB1200ZL 12-OUTPUT PCIE GEN 3 BUFFER

Si53112
1. Electrical Specifications
Table 1. DC Operating Characteristics
V_{DD_A} = 3.3 V±5%, V_DD = 3.3 V±5%
Parameter
Symbol
Test Condition
Min
Max
Unit
3.3 V Core Supply Voltage
3.3 V I/O Supply Voltage¹
VDD/VDD_A
3.3 V ±5%
3.135
3.465
V
VDD_IO 1.05 V to 3.3 V ±5% 0.9975
3.465
V
3.3 V Input High Voltage
3.3 V Input Low Voltage
Input Leakage Current²
3.3 V Input High Voltage³
3.3 V Input Low Voltage³
3.3 V Input Low Voltage
3.3 V Input Med Voltage
3.3 V Input High Voltage
3.3 V Output High Voltage⁴
3.3 V Output Low Voltage⁴
Input Capacitance⁵
Output Capacitance⁵
Pin Inductance
Ambient Temperature
V_IH
V_IL
I_IL
V_{IH_FS}
V_{IL_FS}
V_{IL_Tri}
V_{IM_Tri}
V_{IH_Tri}
V_OH
V_OL
C_IN
C_OUT
L_PIN
T_A
VDD
0 < VIN < VDD
VDD
I_OH = –1 mA
I_OL = 1 mA
No Airflow
2.0
VDD+0.3 V
VSS-0.3
0.8
V
–5
+5
µA
0.7
VDD+0.3 V
VSS–0.3 0.35
V
0
0.8
V
1.2
1.8
V
2.2
VDD
V
2.4
—
V
—
0.4
V
2.5
4.5
pF
2.5
4.5
pF
—
7
nH
–40
85
°C
Notes:
1. VDD_IO applies to the low-power NMOS push-pull HCSL compatible outputs.
2. Input Leakage Current does not include inputs with pull-up or pull-down resistors. Inputs with resistors should state
current requirements.
3. Internal voltage reference is to be used to guarantee V_IH_FS and V_IL_FS thresholds levels over full operating range.
4. Signal edge is required to be monotonic when transitioning through this region.
5. Ccomp capacitance based on pad metallization and silicon device capacitance. Not including pin capacitance.
Table 2. Current Consumption
T_A = –40 to 85 °C; supply voltage V_DD = 3.3 V ±5%
Parameter
Symbol
Test Condition
Min Typ Max Unit
Operating Current IDD_VDD
133 MHz, VDD Rail
—
IDD_VDDA
133 MHz, VDDA + VDDR, PLL Mode —
IDD_VDDIO
133 MHz, CL = Full Load, VDD IO Rail —
Power Down Current IDD_VDDPD Power Down, VDD Rail
—
IDD_VDDAPD Power Down, VDDA Rail
—
IDD_VDDIOPD Power Down, VDD_IO Rail
—
18
25
mA
17
20
mA
85
110 mA
0.4
1
mA
2
5
mA
0.2
0.5
mA
4
Rev. 1.1