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SI53112 Datasheet, PDF (14/35 Pages) Silicon Laboratories – DB1200ZL 12-OUTPUT PCIE GEN 3 BUFFER | |||
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Si53112
2.6. HBW_BYPASS_LBW
The HBW_BYPASS_LBW pin is a tri-level function input pin (refer to Table 13 for VIL_Tri, VIM_Tri, and VIH_Tri
signal levels). It is used to select between PLL high-bandwidth, PLL bypass mode, or PLL low-bandwidth mode. In
PLL bypass mode, the input clock is passed directly to the output stage, which may result in up to 50 ps of additive
cycle-to-cycle jitter (50 ps + input jitter) on the differential outputs. In the case of PLL mode, the input clock is
passed through a PLL to reduce high-frequency jitter. The PLL HBW, BYPASS, and PLL LBW modes may be
selected by asserting the HBW_BYPASS_LBW input pin to the appropriate level described in Table 13.
Table 13. PLL Bandwidth and Readback Table
HBW_BYPASS_LBW Pin
L
M
H
Mode
LBW
BYPASS
HBW
Byte 0, Bit 7
0
0
1
Byte 0, Bit 6
0
1
1
The Si53112 has the ability to override the latch value of the PLL operating mode from hardware strap pin 5 via the
use of Byte 0 and bits 2 and 1. Byte 0 bit 3 must be set to 1 to allow the user to change Bits 2 and 1, affecting the
PLL. Bits 7 and 6 will always read back the original latched value. A warm reset of the system will have to be
accomplished if the user changes these bits.
2.7. Miscellaneous Requirements
Data Transfer Rate: 100 kbps (standard mode) is the base functionality required. Fast mode (400 kbps)
functionality is optional.
Logic Levels: SMBus logic levels are based on a percentage of VDD for the controller and other devices on the
bus. Assume all devices are based on a 3.3 V supply.
Clock Stretching: The clock buffer must not hold/stretch the SCL or SDA lines low for more than 10 ms. Clock
stretching is discouraged and should only be used as a last resort. Stretching the clock/data lines for longer than
this time puts the device in an error/time-out mode and may not be supported in all platforms. It is assumed that all
data transfers can be completed as specified without the use of clock/data stretching.
General Call: It is assumed that the clock buffer will not have to respond to the âgeneral call.â
Electrical Characteristics: All electrical characteristics must meet the standard mode specifications found in
Section 3 of the SMBus 2.0 specification.
Pull-Up Resistors: Any internal resistor pull-ups on the SDATA and SCLK inputs must be stated in the individual
data sheet. The use of internal pull-ups on these pins of below 100 K is discouraged. Assume that the board
designer will use a single external pull-up resistor for each line and that these values are in the 5â6 kï range.
Assume one SMBus device per DIMM (serial presence detect), one SMBus controller, one clock buffer, one clock
driver plus one/two more SMBus devices on the platform for capacitive loading purposes.
Input Glitch Filters: Only fast mode SMBus devices require input glitch filters to suppress bus noise. The clock
buffer is specified as a standard mode device and is not required to support this feature. However, it is considered
a good design practice to include the filters.
PWRDN: If a clock buffer is placed in PWRDN mode, the SDATA and SCLK inputs must be Tri-stated and the
device must retain all programming information. IDD current due to the SMBus circuitry must be characterized and
in the data sheet.
14
Rev. 1.1
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