SI53112-A03A Datasheet, PDF (8/34 Pages) Silicon Laboratories – DB1200ZL 12-OUTPUT PCIE GEN 3 BUFFER

Si53112-A03A
Table 5. DIF 0.7 V AC Timing Characteristics (Non-Spread Spectrum Mode)¹
Parameter
Symbol
CLK 100 MHz, 133 MHz
Clock Stabilization Time²
Long Term Accuracy^2,3,4
Absolute Host CLK Period (100 MHz)^2,3,5
Absolute Host CLK Period (133 MHz)^2,3,5
Edge Rate^2,3,6
Rise Time Variation^2,7,8
Fall Time Variation^2,7,8
Rise/Fall Matching^2,7,9,10
Voltage High (typ 0.7 V)^2,7,11
Voltage Low (typ 0.7 V)^2,7,12
Maximum Voltage^2,7,13,14,15
Absolute Crossing Point Voltages^2,7,15,16
Relative Crossing Point Voltages
Total Variation of Vcross Over All Edges^2,7,17
Duty Cycle^2,3
Maximum Voltage (Overshoot)^2,7,18
Maximum Voltage (Undershoot)^2,7,19
T_STAB
L_ACC
T_ABS
T_ABS
Edge_rate
∆ Trise
∆ Tfall
T_{RISE_MAT}/
T_{FALL_MAT}
V_HIGH
V_LOW
V_MAX
Vox_ABS
Vox_REL
Total ∆ Vox
DC
V_ovs
V_uds
Min
—
—
9.94900
7.44925
1.0
—
—
—
660
–150
—
250
—
45
—
—
Typ
Max
1.5
1.8
100
10.05100
7.55075
4.0
125
125
20
850
150
1150
550
140
55
V_High + 0.3
V_Low – 0.3
Unit
ms
ppm
ns
ns
V/ns
ps
ps
%
mV
mV
mV
mV
mV
%
V
V
8
Rev. 1.0