SI53112-A03A Datasheet, PDF (15/34 Pages) Silicon Laboratories – DB1200ZL 12-OUTPUT PCIE GEN 3 BUFFER

2.8. Buffer Power-Up State Machine
Si53112-A03A
Table 14. Buffer Power-Up State Machine
State
Description
0
3.3 V buffer power is off.
1
After 3.3 V supply is detected to rise above 1.8–2.0 V, the
buffer enters State 1 and initiates a 0.1–0.3 ms delay.
2
Buffer waits for a valid clock on the CLK input and PWRDN
de-assertion.
3
Once the PLL is locked to the CLK_IN input clock, the buffer
enters state 3 and enables outputs for normal operation.
Notes:
1. The total power-up latency from power-on to all outputs active must be less
than 1.8 ms (assuming a valid clock is present on CLK_IN input).
2. If power is valid and power-down is deasserted but no input clocks are
present on the CLK_IN input, DIF clocks must remain disabled. Only after
valid input clocks are detected, valid power, PWRDN deasserted with the
PLL locked/stable are the DIF outputs enabled.
No input clock
S1
Delay
0.1 ms – 0.3 ms
S2
Wait for input
clock and power
down
deassertion
S0
Power Off
Power Down
Asserted
S3
Normal
Operation
Figure 3. Buffer Power-Up State Diagram
Rev. 1.0
15