SI53112-A03A Datasheet, PDF (1/34 Pages) Silicon Laboratories – DB1200ZL 12-OUTPUT PCIE GEN 3 BUFFER

Si53112-A03A
DB1200ZL 12-OUTPUT PCIE GEN 3 BUFFER
Features
 Twelve 0.7 V low-power, push-  PLL or bypass mode
pull, HCSL-compatible
 Spread spectrum tolerable
PCIe Gen 3 outputs
 1.05 to 3.3 V I/O supply voltage


Individual OE HW pins for each
output clock
100 MHz /133 MHz PLL
operation, supports PCIe and
QPI



50 ps output-to-output skew
50 ps cyc-cyc jitter (PLL mode)
Low phase jitter (Intel QPI, PCIe
Gen 1/2/3/4 common clock
compliant)

PLL bandwidth SW SMBUS
programming overrides the latch

Gen 3 SRNS Compliant
value from HW pin
 100 ps input-to-output delay


9 selectable SMBUS addresses
SMBus address configurable to
allow multiple buffers in a single


Extended Temperature:
–40 to 85 °C
Package: 64-pin QFN
control network 3.3 V supply ^{ For higher output devices or}
voltage operation
variations of this device, contact
 Integrated termination resistors
Silicon Labs
supporting 85 transmission
lines
Applications
 Server
 Storage
 Data center
 Enterprise Switches and Routers
Description
The Si53112-A03A is a low-power, 12-output, differential clock buffer that
meets all of the performance requirements of the Intel DB1200ZL
specification. To reduce board space and bill of material cost, the device
fully integrates all external resistors, supporting 85 transmission lines.
The device is optimized for distributing reference clocks for Intel^®
QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/Gen 3/Gen 4,
SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI)
applications. The VCO of the device is optimized to support 100 MHz and
133 MHz operation. Each differential output has a dedicated hardware
output enable pin for maximum flexibility and power savings. Measuring
PCIe clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter
Tool. Download it for free at www.silabs.com/pcie-learningcenter.
Ordering Information:
See page 30.
Patents pending
Rev. 1.0 12/15
Copyright © 2015 by Silicon Laboratories
Si53112-A03A