SI53112-A03A Datasheet, PDF (6/34 Pages) Silicon Laboratories – DB1200ZL 12-OUTPUT PCIE GEN 3 BUFFER

Si53112-A03A
Table 4. Phase Jitter
Parameter
Phase Jitter
PLL Mode
Test Condition
Min
PCIe Gen 1, Common Clock^1,2,3
—
PCIe Gen 2 Low Band, Common Clock
—
F < 1.5 MHz^1,3,4,5
PCIe Gen 2 High Band, Common Clock
—
1.5 MHz < F < Nyquist^1,3,4,5
PCIe Gen 3, Common Clock
—
(PLL BW 2–4 MHz, CDR = 10 MHz)^1,3,4,5
PCIe Gen 3 Separate Reference No Spread, SRNS —
(PLL BW of 2–4 or 2–5 MHz, CDR = 10 MHz)^1,3,4,5
PCIe Gen 4, Common Clock
—
(PLL BW of 2–4 or 2–5 MHz, CDR = 10 MHz)^1,4,5,8
Intel^® QPI & Intel SMI
—
(4.8 Gbps or 6.4 Gb/s, 100 or 133 MHz, 12 UI)^1,6,7
Intel QPI & Intel SMI
—
(8 Gb/s, 100 MHz, 12 UI)^1,6
Intel QPI & Intel SMI
—
(9.6 Gb/s, 100 MHz, 12 UI)^1,6
Typ
29
2.0
1.9
0.45
0.32
0.45
0.21
0.13
0.11
Max Unit
86
ps
3.0
ps
(RMS)
3.1
ps
(RMS)
1.0
ps
(RMS)
0.71
ps
(RMS)
1.0
ps
(RMS)
0.5
ps
(RMS)
0.3
ps
(RMS)
0.2
ps
(RMS)
Notes:
1. Post processed evaluation through Intel supplied Matlab* scripts. Defined for a BER of 1E-12. Measured values at a
smaller sample size have to be extrapolated to this BER target.
2. ζ = 0.54 implies a jitter peaking of 3 dB.
3. PCIe* Gen3 filter characteristics are subject to final ratification by PCISIG. Check the PCI-SIG for the latest
specification.
4. Measured on 100 MHz PCIe output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3.
5. Measured on 100 MHz output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3.
6. Measured on 100 MHz, 133 MHz output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3.
7. These jitter numbers are defined for a BER of 1E-12. Measured numbers at a smaller sample size have to be
extrapolated to this BER target.
8. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
9. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.
6
Rev. 1.0