SI53112-A03A Datasheet, PDF (29/34 Pages) Silicon Laboratories – DB1200ZL 12-OUTPUT PCIE GEN 3 BUFFER

Pin #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Si53112-A03A
Table 24. si53112-A03A 64-Pin QFN Descriptions
Name
DIF_8
OE_8
OE_9
DIF_9
DIF_9
VDD_IO
VDD
GND
DIF_10
DIF_10
OE_10
OE_11
DIF_11
DIF_11
Type
Description
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
I, SE 3.3 V LVTTL active low input for enabling differential outputs (default).
Controls the corresponding output pair. Internal pull-down.
I, SE 3.3 V LVTTL active low input for enabling differential outputs (default).
Controls the corresponding output pair. Internal pull-down.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
VDD Power supply for differential outputs.
3.3 V 3.3 V power supply for outputs.
GND Ground for outputs.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
I, SE 3.3 V LVTTL active low input for enabling differential outputs (default).
Controls the corresponding output pair. Internal pull-down.
I, SE 3.3 V LVTTL active low input for enabling differential outputs (default).
Controls the corresponding output pair. Internal pull-down.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
O, DIF 0.7 V Differential clock outputs. Default is 1:1.
Rev. 1.0
29