SI4770-77-A20 Datasheet, PDF (8/54 Pages) Silicon Laboratories – HIGH-PERFORMANCE CONSUMER ELECTRONICS

Si4770/77-A20
Table 4. Digital Zero-IF I/Q Interface Characteristics (Si4777 Only)¹
(T_AMB = –40 to 85 °C, V_A = 4.5 to 5.5 V, V_D = 2.7 to 3.6 V, V_IO1 = 1.7 to 3.6 V, V_IO2 = 1.2 to 3.6 V)
Parameter
Symbol
IQCLK Output Cycle Time
IQCLK Output Pulse Width High
IQCLK Output Pulse Width Low
IQFS Output Delay
IQFS Output Setup to IQCLK
Rise³
t_CYC:IQCLK
t_HI:IQCLK
t_LO:IQCLK
t_PD:IQFS
t_SU:IQFS
IOUT Output Delay
QOUT Output Delay
IOUT Output Setup to IQCLK rise³
QOUT Output Setup to IQCLK
Rise³
t_PD:IOUT
t_PD:QOUT
t_SU:IOUT
t_SU:QOUT
Test
Min
Typ
Max
Unit
Condition
0.8 x per
per²
1.2 x per
ns
0.22 x per
—
0.59 x per
ns
0.41 x per
—
0.78 x per
ns
0
— (0.5 x per) + 18 ns
(0.5 x per) – 18 —
—
ns
0
— (0.5 x per) + 18 ns
0
— (0.5 x per) + 18 ns
(0.5 x per) – 18 —
—
ns
(0.5 x per) – 18 —
—
ns
Notes:
1. Guaranteed by characterization.
2. per is the IQCLK I/Q bit clock period. Refer to Table 15 on page 35 for IQCLK bit clock frequencies.
3. Minimum time the Si4770/77-A20 will produce between valid output and the next rising edge of IQCLK
IQCLK out
IQFS out
t_CYC:IQCLK Max
t_CYC:IQCLK Min
t_HI:IQCLK MIN
t_HI:IQCLK MAX
t_PD:IQFS MAX
t_PD:IQFS MIN
t_LO:IQCLK MAX
t_LO:IQCLK MIN
t_SU:IQFS
IOUT out
t_PD:IOUT MAX
t_PD:IOUT MIN
t_SU:IOUT
QOUT out
t_PD:QOUT MAX
t_PD:QOUT MIN
t_SU:QOUT
Figure 2. Digital Zero-IF I/Q
8
Rev. 0.9