SI4770-77-A20 Datasheet, PDF (43/54 Pages) Silicon Laboratories – HIGH-PERFORMANCE CONSUMER ELECTRONICS

Si4770/77-A20
5. RDS/RBDS Advanced Processor 6. Programming Section
The Si4770/77-A20 implements an advanced, patented,
high-performance RDS processor for demodulation,
symbol decoding, block synchronization, error
detection, and error correction. The RDS decoder
applies advanced decoding and statistical decision
techniques
to
provide
high-performance
synchronization at very noisy signal levels, and
excellent sensitivity at industry-standard block error rate
(BLER) levels (5%).
The Si4770/77-A20’s strong synchronization
performance in very noisy/low SNR environments
minimizes the number of instances of lost
synchronization. Other less robust tuners must attempt
to resynchronize in low SNR environments, resulting in
lost data and lengthy delays in reestablishing data
reception.
The
Si4770/77-A20
maintains
synchronization to the RDS transmission, despite high
BLER. This results in fewer dropped connections,
minimal resynchronization time, and greater data
reliability in low SNR environments.
The Si4770/77-A20 reports RDS decoder
synchronization status and detailed bit errors for each
RDS block. The range of reportable bit errors detected
and corrected are 0, 1-2, 3-5, and “not correctable.”
More than five errors indicate that the corresponding
block information word is non-correctable.
The Si4770/77-A20 also provides highly configurable
interrupts based on RDS-driven events and conditions.
The default settings provide an interrupt when RDS is
synchronized and when RDS group data has been
received. The configurable interrupts can be set to
provide frequent interrupts down to a single received
block with BLER. The configurable interrupts also can
be set to provide very infrequent interrupts, buffering up
to 25 complete RDS groups (100 blocks) with BLER
information by block in the on-chip FIFO. The Si4770/
77-A20 also provides configurable interrupts on
changes or receipt of the key RDS blocks A and B. This
flexibility allows adopters to either conduct extensive
RDS data processing on the host or reserve the host
processor in power-saving modes with minimal RDS
interrupts, allowing the Si4770/77-A20 to perform RDS
processing on-chip.
To ease development time and offer maximum
customization, the Si4770/77-A20 provides a simple
and powerful software command protocol in addition to
the 2-wire I²C serial interface to communicate with the
host processor.The device is programmed using
commands, arguments, properties, and responses. To
perform an action, the user writes a command byte and
associated arguments, causing the chip to execute the
given command. Commands control actions such as
powerup, powerdown, or tune to a station. Arguments
are specific to a given command and are used to modify
the command. Properties are a special command +
argument used to modify the default chip operation and
are generally configured immediately after powerup.
Examples of properties are de-emphasis level, RSSI
seek threshold, and soft mute attenuation threshold.
Responses provide information and are echoed after a
command + argument is issued and processed. All
commands provide a one-byte status update indicating
interrupt and clear-to-send status information.
Rev. 0.9
43