SLWSTK6000A Datasheet, PDF (7/80 Pages) Silicon Laboratories – ConfidentialMighty Gecko Wireless SoC EFR32MG1X232

EFR32MG1X232 Data Sheet
System Overview
3.3.8 Flexible Frame Handling
Confidential ^{EFR32MG1X232 has an extensive and flexible frame handling support for easy implementation of even complex communication proto-}
cols. The Frame Controller (FRC) supports all low level and timing critical tasks together with the Radio Controller and Modulator/
Demodulator:
• Highly adjustable preamble length
• Up to 2 simultaneous synchronization words, each up to 32 bits and providing separate interrupts
• Frame disassembly and address matching (filtering) to accept or reject frames
• Automatic ACK frame assembly and transmission
• Fully flexible CRC generation and verification:
• Multiple CRC values can be embedded in a single frame
• 8, 16, 24 or 32-bit CRC value
• Configurable CRC bit and byte ordering
• Selectable bit-ordering (least significant or most significant bit first)
• Optional data whitening
• Optional Forward Error Correction (FEC), including convolutional encoding / decoding and block encoding / decoding
• Half rate convolutional encoder and decoder with constraint lengths from 2 to 7 and optional puncturing
• Fully configurable block codes for sub-GHz protocols, supporting both linear codes and table based lookup (e.g. Wireless M-bus 3-
out-of-6 coding)
• Optional symbol interleaving, typically used in combination with FEC
• Symbol coding, such as Manchester or DSSS, supported in the MODEM, or biphase space encoding using FEC hardware
• UART encoding over air, with start and stop bit insertion / removal
• Test mode support, such as modulated or unmodulated carrier output
• Received frame timestamping
3.3.9 Packet and State Trace
The EFR32MG1X232 Frame Controller has a packet and state trace unit that provides valuable information during the development
phase. It features:
• Non-intrusive trace of transmit data, receive data and state information
• Data observability on a single-pin UART data output, or on a two-pin SPI data output
• Configurable data output bitrate / baudrate
• Multiplexed transmitted data, received data and state / meta information in a single serial data stream
3.3.10 Data Buffering
The EFR32MG1X232 features an advanced buffer controller (BUFC) capable of handling up to 4 buffers of adjustable size from 64
bytes to 4096 bytes. Each buffer can be used for RX, TX or both. The buffer data is located in RAM, enabling zero-copy operations.
3.3.11 Radio Controller (RAC)
The Radio Controller controls the top level state of the radio subsystem in the EFR32MG1X232. It performs the following tasks:
• Precisely-timed control of enabling and disabling of the receiver and transmitter circuitry
• Run-time calibration of receiver, transmitter and frequency synthesizer
• Detailed frame transmission timing, including optional LBT or CSMA-CA
3.3.12 Crypto Accelerator (CRYPTO)
The Crypto Accelerator is a fast and energy-efficient autonomous hardware encryption and decryption accelerator. EFR32 devices sup-
port various levels of hardware-accelerated encryption, depending on the part. Section 2. Ordering Information specifies whether this
part has full or AES-only crypto support. AES-only devices support AES encryption and decryption with 128- or 256-bit keys. Full cryp-
to support adds RSA-2048, ECC over both GF(P) and GF(2^m), SHA-1 and SHA-2.
Supported modes of operation for AES includes ECB, CTR, CBC, PCBC, CFB, OFB, CBC-MAC, GMAC, CCM and GCM.
Supported ECC NIST recommended curves include P-192, P-224, P-256, K-163, K-233, B-163 and B-233.
The CRYPTO is tightly linked to the BUFC enabling fast and efficient autonomous cipher operations on data buffer content. It allows
fast processing of ECC, RSA and SHA with little CPU intervention. CRYPTO also provides trigger signals for DMA read and write oper-
ations.
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