SLWSTK6000A Datasheet, PDF (12/80 Pages) Silicon Laboratories – ConfidentialMighty Gecko Wireless SoC EFR32MG1X232

EFR32MG1X232 Data Sheet
System Overview
3.3.37.1 DC-DC Converter Powertrain
Confidential ^{The powertrain consists of low-resistance P-channel (PFET1) and N-channel (NFET) switches, combined with a current limiter and}
zero-crossing detector. The power switches provide programmable drive strength by selection of a number of slices for each switch.
The switching logic takes either a PWM signal from a low-noise controller or pulses from a low-power controller and drives PFET1 and
NFET switches using proper dead-time control. The powertrain can switch in both forced Continuous Conduction Mode (CCM) mode
and load-adaptive Continuous Conduction/Discontinuous Conduction (CCM/DCM) mode. Load-adaptive CCM/DCM mode has superior
efficiency in light load conditions, whereas forced CCM mode provides the best transient response and noise control when the radio is
on.
The DC-DC converter includes a current limiter to protect PFET1 from large transient currents. Whenever a current overload is detec-
ted, the switching logic advances the transition from PFET1 to NFET and optionally sends an interrupt signal to the processor.
A zero-voltage detector is included to prevent reverse current in DCM mode. When NFET is on and zero voltage is detected across
NFET, the switching logic will turn NFET off to prevent reverse current. The zero-voltage detector can be disabled to enable forced
CCM mode. It can also be configured as a programmable reverse current limiter.
3.3.37.2 DC-DC Converter Low Noise (LN) Controller
The LN controller consists of an active-RC type-III compensator, a ramp generator and a PWM comparator. The compensator gener-
ates an error voltage from on-chip feedback, which is compared against a ramp voltage by the PWM comparator. The resulting PWM
signal is duty-cycle limited between 3% and 96%, with circuitry to avoid control-loop lockout. The PWM frequency can be generated
from the ramp generator's oscillator or from an external clock from the radio's RF synthesizer. Noise mitigation hardware post-process-
es the PWM signal to avoid in-band noise coupling into the radio system.
3.3.37.3 DC-DC Converter Low Power (LP) Controller
The LP controller consists of a continuous-time comparator with hysteresis and a constant frequency pulse generator. When the output
voltage is lower than the low threshold of the comparator, the pulse generator is enabled to activate the powertrain. The powertrain
switches at a constant-frequency with a fixed duty cycle of about 90%. When the DC-DC output exceeds the comparator's high thresh-
old, the pulse generator is disabled until the cycle starts over again on the next low-threshold crossing. The comparator has four pro-
grammable response-time settings. The lowest setting consumes only approximately 50nA, providing high-efficiency regulation of cur-
rent loads down to the micro-ampere range.
3.4 Configuration Summary
The features of the EFR32MG1X232 is a subset of the feature set described in the EFR32 Reference Manual. Table 3.1 Configuration
Summary on page 11 describes device specific implementation of the features. Remaining modules support full configuration.
Table 3.1. Configuration Summary
Module
USART0
USART1
TIMER0
TIMER1
Configuration
IrDA I²S SmartCard
IrDA I²S SmartCard
with DTI.
Pin Connections
US0_TX, US0_RX, US0_CLK, US0_CS
US1_TX, US1_RX, US1_CLK, US1_CS
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIM1_CC[3:0]
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