SLWSTK6000A Datasheet, PDF (5/80 Pages) Silicon Laboratories – ConfidentialMighty Gecko Wireless SoC EFR32MG1X232

EFR32MG1X232 Data Sheet
System Overview
3.3.2 Integrated Oscillators
Confidential ^{The EFR32MG1X232 supports two crystal oscillators and fully integrates four RC oscillators, listed below.}
• A high frequency crystal oscillator (HFXO) with integrated load capacitors, tunable in small steps, provides a precise timing refer-
ence for the radio and MCU. Crystal frequencies in the range from 38 to 40 MHz are supported. Silicon Laboratories reference de-
signs employ a crystal frequency of 38.4 MHz. An external clock source such as a TCXO can also be applied to the HFXO input for
improved accuracy over temperature.
• An optional 32.768 kHz crystal oscillator (LFXO) can be used as an accurate timing reference in low energy modes.
• A 32.768 kHz crystal oscillator (LFXO) should be used as an accurate timing reference in Bluetooth Smart low energy modes.
• An integrated high frequency RC oscillator (HFRCO) is available for the MCU system, when crystal accuracy is not required. The
HFRCO employs fast startup at minimal energy consumption combined with a wide frequency range.
• An integrated auxilliary high frequency RC oscillator (AUXHFRCO) is available for timing the general-purpose ADC and the Serial
Wire debug port with a wide frequency range.
• An integrated low frequency 32.768 kHz RC oscillator (LFRCO) can be used as a timing reference in low energy modes, when crys-
tal accuracy is not required.
• An integrated ultra-low frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy con-
sumption in low energy modes.
3.3.3 Fractional-N Frequency Synthesizer
The EFR32MG1X232 contains a high performance, low phase noise, fully integrated fractional-N frequency synthesizer. The synthesiz-
er is used in receive mode to generate the LO frequency used by the down-conversion mixer. It is also used in transmit mode to directly
generate the modulated RF carrier.
The fractional-N architecture provides excellent phase noise performance combined with frequency resolution better than 100 Hz, with
low energy consumption. The synthesizer has fast frequency settling which allows very short receiver and transmitter wake up times to
optimize system energy consumption.
3.3.4 Receiver Architecture
The EFR32MG1X232 uses a low-IF receiver architecture, consisting of a Low-Noise Amplifier (LNA) followed by an I/Q down-conver-
sion mixer, emplying a 38.4 MHz crystal reference. The I/Q signals are further filtered and amplified before being sampled by the IF
analog-to-digital converter (IFADC).
The IF frequency is configurable from 150 kHz to 1371 kHz. The IF can further be configured for high-side or low-side injection, provid-
ing flexibility with respect to known interferers at the image frequency.
The Automatic Gain Control (AGC) module adjusts the receiver gain to optimize performance and avoid saturation for excellent selec-
tivity and blocking performance.
Demodulation is performed in the digital domain. The demodulator performs configurable decimation and channel filtering to allow re-
ceive bandwidths ranging from 0.1 to 2530 kHz. High carrier frequency and baud rate offsets are tolerated by active estimation and
compensation. Advanced features supporting high quality communication under adverse conditions include forward error correction by
block and convolutional coding as well as Direct Sequence Spread Spectrum (DSSS).
A Received Signal Strength Indicator (RSSI) is available for signal quality metrics, for level-based proximity detection, and for RF chan-
nel access by Collision Avoidance (CA) or Listen Before Talk (LBT) algorithms. An RSSI capture value with dB resolution is associated
with each received frame and the dynamic RSSI measurement can be monitored throughout reception.
The EFR32MG1X232 features integrated support for antenna diversity to improve link budget, using complementary control outputs to
an external switch. Internal configurable hardware controls automatic switching between antennae during RF receive detection opera-
tions.
In typical applications, the demodulator output is stored in internal buffer memory for access by the MCU. Direct mode supports direct
serial output of demodulated data on configured GPIO pins.
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