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SI570 Datasheet, PDF (7/26 Pages) Silicon Laboratories – ANY-RATE I2C PROGRAMMABLE XO/VCXO
Si570/Si571
Table 4. CLK± Output Levels and Symmetry
Parameter
LVPECL Output Option1
LVDS Output Option2
Symbol
VO
VOD
VSE
VO
Test Condition
mid-level
swing (diff)
swing (single-ended)
mid-level
Min
VDD – 1.42
1.1
0.55
1.125
Typ
—
—
—
1.20
Max Units
VDD – 1.25 V
1.9
VPP
0.95
VPP
1.275
V
VOD
swing (diff)
0.5
0.7
0.9
VPP
CML Output Option2
VO
VOD
mid-level
swing (diff)
—
VDD – 0.75
—
V
0.70
0.95
1.20
VPP
CMOS Output Option3
VOH
VOL
IOH = 32 mA
IOL = 32 mA
0.8 x VDD
—
—
—
VDD
V
0.4
LVPECL/LVDS/CML
—
Rise/Fall time (20/80%)
tR, tF
CMOS with CL = 15 pF
—
—
350
ps
1
—
ns
LVPECL: VDD – 1.3 V (diff)
Symmetry (duty cycle)
SYM LVDS: 1.25 V (diff)
45
—
55
%
CMOS: VDD/2
Notes:
1. 50 Ω to VDD – 2.0 V.
2. Rterm = 100 Ω (differential).
3. CL = 15 pF
Table 5. CLK± Output Phase Jitter (Si570)
Parameter
Phase Jitter (RMS)*
for FOUT > 500 MHz
Phase Jitter (RMS)*
for FOUT of 125 to 500 MHz
Symbol
Test Condition
Min
φJ
12 kHz to 20 MHz (OC-48)
—
50 kHz to 80 MHz (OC-192)
—
φJ
12 kHz to 20 MHz (OC-48)
—
50 kHz to 20 MHz (OC-192)
—
*Note: Differential Modes: LVPECL/LVDS/CML. Refer to AN256 for further information.
Typ
0.25
0.26
0.36
0.34
Max
0.40
0.37
0.50
0.42
Units
ps
ps
Rev. 0.3
7