SI570 Datasheet, PDF (21/26 Pages) Silicon Laboratories – ANY-RATE I2C PROGRAMMABLE XO/VCXO

Si570/Si571
7. Ordering Information
The Si570/Si571 supports a wide variety of options including frequency range, start-up frequency, temperature
stability, tuning slope, output format, and V_DD. Specific device configurations are programmed into the Si570/Si571
at time of shipment. Configurations are specified using the Part Number Configuration chart shown below. Silicon
Labs provides a web browser-based part number configuration utility to simplify this process. Refer to
www.silabs.com/VCXOPartNumber to access this tool and for further ordering instructions. The Si570/Si571 XO/
VCXO series is supplied in an industry-standard, RoHS compliant, Pb-free, 8-pad, 5 x 7 mm package. Tape and
reel packaging is an ordering option.
57x
X
X
X XXX XXX D
G
R
R = Tape & Reel
Blank = Trays
570 Programmable
XO Product Family
Operating Temp Range (°C)
G
–40 to +85 °C
571 Programmable
VCXO Product Family
1^st Option Code
VDD Output Format Output Enable Polarity
A 3.3 LVPECL
High
B 3.3 LVDS
High
C 3.3 CMOS
High
D 3.3 CML
High
E 2.5 LVPECL
High
F 2.5 LVDS
High
G 2.5 CMOS
High
H 2.5 CML
High
J 1.8 CMOS
High
K 1.8 CML
High
M 3.3 LVPECL
Low
N 3.3 LVDS
Low
P 3.3 CMOS
Low
Q 3.3 CML
Low
R 2.5 LVPECL
Low
S 2.5 LVDS
Low
T 2.5 CMOS
Low
U 2.5 CML
Low
V 1.8 CMOS
Low
W 1.8 CML
Low
Note:
CMOS available to 160 MHz.
Device Revision Letter
Six-Digit Start-up Frequency/I²C Address Designator
The Si57x supports a user-defined start-up frequency within the following
bands of frequencies: 10–945 MHz, 970–1134 MHz, and 1213–1417 MHz.
The start-up frequency must be in the same frequency range as that
specified by the Frequency Grade 3^rd option code.
The Si57x supports a user-defined I²C 7-bit address. Each unique start-up
frequency/I²C address combination is assigned a six-digit numerical code.
This code can be requested during the part number request process. Refer
to www.silabs.com/VCXOPartNumber to request an Si57x part number.
3^rd Option Code
Frequency Grade
Code
A
B
C
Frequency Range Supported (MHz)
10-945, 970-1134, 1213-1417.5
10-810
10-215
Si570
Code
A
B
2^nd Option Code
Temperature Stability (ppm, max, ±) Total Stablility (ppm, max, ±)
50
61.5
20
31.5
2^nd Option Code
Si571
Temperature Tuning Slope
Minimum APR
Stability
Kv
(±ppm) for VDD @
Code ± ppm (max) ppm/V (typ)
3.3 V
2.5 V
1.8 V
A
100
180
100
75
25
B
100
90
30
Note 6
Note 6
C
50
180
150
125
75
D
50
90
80
30
25
E
20
45
25
Note 6 Note 6
F
50
135
100
75
50
G
20
356
375
300
235
H
20
180
185
145
105
J
20
135
130
104
70
K
100
356
295
220
155
M
20
33
12
Note 6 Note 6
Notes:
1. For best jitter and phase noise performance, always choose the smallest Kv that meets
the application’s minimum APR requirements. Unlike SAW-based solutions which
require higher higher Kv values to account for their higher temperature dependence,
the Si55x series provides lower Kv options to minimize noise coupling and jitter in real-
world PLL designs. See AN255 and AN266 for more information.
2. APR is the ability of a VCXO to track a signal over the product lifetime. A VCXO with an
APR of ±25 ppm is able to lock to a clock with a ±25 ppm stability over 15 years over all
operating conditions.
3. Nominal Pull range (±) = 0.5 x VDD x tuning slope.
4. Nominal Absolute Pull Range (±APR) = Pull range – stability – lifetime aging
= 0.5 x VDD x tuning slope – stability – 10 ppm
5. Minimum APR values noted above include worst case values for all parameters.
6. Combination not available.
Figure 4. Part Number Convention
Rev. 0.3
21