SI570 Datasheet, PDF (5/26 Pages) Silicon Laboratories – ANY-RATE I2C PROGRAMMABLE XO/VCXO

Si570/Si571
2. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol Test Condition
Min
Typ
Max Units
3.3 V option
2.97
3.3
3.63
Supply Voltage¹
V_DD
2.5 V option
1.8 V option
2.25
2.5
2.75
V
1.71
1.8
1.89
Supply Current
Output enabled
LVPECL
—
120
130
CML
I_DD
LVDS
—
108
117
—
99
108
mA
CMOS
—
90
98
TriState mode
—
60
75
Output Enable (OE)²
V_IH
0.75 x V_DD
—
—
V
V_IL
—
—
0.5
Operating Temperature Range
T_A
–40
—
85
ºC
Notes:
1. Selectable parameter specified by part number. See Section "7. Ordering Information" on page 21 for further details.
2. OE pin includes a 17 kΩ pullup resistor to V_DD or a 17 kΩ pulldown to GND depending on the OE polarity specified in
the part number. See "7. Ordering Information" on page 21.
Table 2. V_C Control Voltage Input
Parameter
Symbol Test Condition
Min
Typ
Max Units
33
45
Control Voltage Tuning Slope^1,2,3
K_V
V_C 10 to 90% of V_DD
—
90
135
—
ppm/V
180
356
Control Voltage Linearity⁴
BSL
–5
±1
+5
L_VC
Incremental
%
–10
±5
+10
Modulation Bandwidth
BW
9.3
10.0
10.7
kHz
V_C Input Impedance
Nominal Control Voltage
Z_VC
V_CNOM
@ f_O
500
—
—
kΩ
—
V_DD/2
—
V
Control Voltage Tuning Range
V_C
0
V_DD
V
Notes:
1. Positive slope; selectable option by part number. See "7. Ordering Information" on page 21.
2. For best jitter and phase noise performance, always choose the smallest K_V that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (K_V), Stability, and Absolute Pull Range (APR)” for more information.
3. K_V variation is ±10% of typical values.
4. BSL determined from deviation from best straight line fit with V_C ranging from 10 to 90% of V_DD. Incremental slope
determined with V_C ranging from 10 to 90% of V_DD.
Rev. 0.3
5