SI570 Datasheet, PDF (10/26 Pages) Silicon Laboratories – ANY-RATE I2C PROGRAMMABLE XO/VCXO

Si570/Si571
Table 8. Typical CLK± Output Phase Noise (Si570)
Offset Frequency (f)
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
100 MHz
120.00 MHz
LVDS
–112
–122
–132
–137
–144
–150
n/a
156.25 MHz
LVPECL
–105
–122
–128
–135
–144
–147
n/a
622.08 MHz
LVPECL
–97
–107
–116
–121
–134
–146
–148
Units
dBc/Hz
Table 9. Typical CLK± Output Phase Noise (Si571)
Offset Frequency
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
100 MHz
74.25 MHz
90 ppm/V
LVPECL
–87
–114
–132
–142
–148
–150
n/a
491.52 MHz
45 ppm/V
LVPECL
–75
–100
–116
–124
–135
–146
–147
622.08 MHz
135 ppm/V
LVPECL
–65
–90
–109
–121
–134
–146
–147
Units
dBc/Hz
Table 10. Absolute Maximum Ratings
Parameter
Symbol
Rating
Units
Supply Voltage
Input Voltage
Storage Temperature
ESD Sensitivity (HBM, per JESD22-A114)
V_DD
V_I
T_S
ESD
–0.5 to +3.8
–0.5 to V_DD + 0.3
–55 to +125
>2500
Volts
Volts
ºC
Volts
Soldering Temperature (lead-free profile)
T_PEAK
260
ºC
Soldering Temperature Time @ T_PEAK (lead-free profile)
t_P
20–40
seconds
Notes:
1. Stresses beyond the absolute maximum ratings may cause permanent damage to the device. Functional operation or
specification compliance is not implied at these conditions.
2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at
www.silabs.com/VCXO for further information, including soldering profiles.
10
Rev. 0.3