SI5368 Datasheet, PDF (7/18 Pages) Silicon Laboratories – ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

2. Pin Descriptions: Si5368
Si5368
NC
NC
RST
NC
VDD
VDD
GND
GND
C1B
C2B
C3B
INT_ALM
CS0_C3A
GND
VDD
XA
XB
GND
GND
NC
FS_ALIGN
NC
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
2
74
3
73
4
72
5
71
6
70
7
69
8
68
9
67
10
66
11
65
12
13
64
Si5368
63
14
62
15
61
16
60
17
59
18
GND PAD
58
19
57
20
56
21
55
22
54
23
53
24
52
25
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ^{41 42 43 44 45 46 47 48 49 50}
NC
NC
NC
NC
SDI
A2_SS
A1
A0
NC
NC
GND
GND
VDD
VDD
SDA_SDO
SCL
C2A
C1A
CS1_C4A
NC
INC
DEC
NC
NC
NC
Table 3. Si5368 Pin Descriptions
Pin #
1, 2, 4, 20,
22, 23, 24,
25, 37, 47,
48, 50, 51,
52, 53, 56,
66, 67, 72,
73, 74, 75,
80, 85, 95
Pin Name
NC
I/O Signal Level
Description
No Connect.
These pins must be left unconnected for normal operation.
3
RST
I LVCMOS External Reset.
Active low input that performs external hardware reset of
device. Resets all internal logic to a known state and forces the
device registers to their default value. Clock outputs are
tristated during reset. After rising edge of RST signal, the device
will perform an internal self-calibration.
This pin has a weak pull-up.
Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map.
Preliminary Rev. 0.3
7