SI5368 Datasheet, PDF (1/18 Pages) Silicon Laboratories – ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5368
PRELIMINARY DATA SHEET
ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR
Description
The Si5368 is a jitter-attenuating precision clock multiplier for
applications requiring sub 1 ps rms jitter performance. The
Si5368 accepts four clock inputs ranging from 2 kHz to
710 MHz and generates five independent, synchronous clock
outputs ranging from 2 kHz to 945 MHz and select
frequencies to 1.4 GHz. The device provides virtually any
frequency translation combination across this operating
range. The outputs are divided down separately from a
common source. The Si5368 input clock frequency and clock
multiplication ratio are programmable through an I²C or SPI
interface. The Si5368 is based on Silicon Laboratories' 3rd-
generation DSPLL^® technology, which provides any-rate
frequency synthesis and jitter attenuation in a highly
integrated PLL solution that eliminates the need for external
VCXO and loop filter components. The DSPLL loop
bandwidth is digitally programmable, providing jitter
performance optimization at the application level. Operating
from a single 1.8 or 2.5 V supply, the Si5368 is ideal for
providing clock multiplication and jitter attenuation in high
performance timing applications.
Applications
SONET/SDH OC-48/OC-192 line cards
GbE/10GbE, 1/2/4/8/10GFC line cards
ITU G.709 and custom FEC line cards
Wireless basestations
Data converter clocking
xDSL
SONET/SDH + PDH clock synthesis
Test and measurement
Features
Generates any frequency from 2 kHz to 945 MHz
and select frequencies to 1.4 GHz from an input
frequency of 2 kHz to 710 MHz
Ultra-low jitter clock outputs w/jitter generation as
low as 0.3 ps rms (50 kHz–80 MHz)
Integrated loop filter with selectable loop bandwidth
(60 Hz to 8.4 kHz)
Meets OC-192 GR-253-CORE jitter specifications
Four clock inputs w/manual or automatically
controlled hitless switching
Five clock outputs with selectable signal format
(LVPECL, LVDS, CML, CMOS)
SONET frame sync switching and regeneration
Support for ITU G.709 and custom FEC ratios
(255/238, 255/237, 255/236)
LOL, LOS, FOS alarm outputs
Digitally-controlled output phase adjust
I²C or SPI programmable settings
On-chip voltage regulator for 1.8 or 2.5 V ±10%
operation
Small size: 14 x 14 mm 100-pin TQFP
Pb-free, RoHS compliant
CKIN1
CKIN2
CKIN3
CKIN4
I²C/SPI Port
Rate Select
Clock Select
Latency Control
FSYNC Realignment
Device Interrupt
LOL/LOS/FOS Alarms
÷ N31
÷ N32
÷ N33
÷ N34
Control
Xtal or Refclock
DSPLL^®
÷ NC1
÷ NC2
÷ N2
÷ NC3
÷ NC4
Output Clock 2
Input Clock 3
Input Clock 4
÷ NFS
CKOUT1
CKOUT2
CKOUT3
CKOUT4
CKOUT5/FS_OUT
VDD (1.8 or 2.5 V)
GND
Preliminary Rev. 0.3 3/07
Copyright © 2007 by Silicon Laboratories
Si5368
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.