SI5368 Datasheet, PDF (2/18 Pages) Silicon Laboratories – ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5368
Table 1. Performance Specifications
(V_DD = 1.8 or 2.5 V ±10%, T_A = –40 to 85 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
Temperature Range
T_A
Supply Voltage
V_DD
–40
25
85
ºC
2.25
2.5
2.75
V
1.62
1.8
1.98
V
Supply Current
I_DD
f_OUT = 622.08 MHz
—
All CKOUTs enabled LVPECL
format output
394
435
mA
Only CKOUT1 enabled
—
253
284
mA
f_OUT = 19.44 MHz
All CKOUTs enabled
CMOS format output
—
278
321
mA
Only CKOUT1 enabled
—
229
261
mA
Tristate/Sleep Mode
—
TBD TBD
mA
Input Clock Frequency
(CKIN1, CKIN2, CKIN3,
CK_F Input frequency and clock mul- 0.002
—
tiplication ratio determined by
710
MHz
CKIN4)
programming device PLL divid-
Input Clock Frequency
(CKIN3, CKIN4 used as
FSYNC inputs)
CK_F
ers. Consult Silicon Laborato-
ries configuration software
0.002
—
0.512 MHz
DSPLLsim or Any-Rate Preci-
sion Clock Family Reference
Output Clock Frequency
CK_{OF Manual at www.silabs.com/tim-} 0.002
—
945
MHz
(CKOUT1, CKOUT2,
ing to determine PLL divider
970
—
1134
CKOUT3, CKOUT4, CKOUT5
settings for a given input fre- 1213
—
1417
used as fifth high-speed out-
quency/clock multiplication
put)
ratio combination.
CKOUT5 used as frame sync CK_OF
output (FS_OUT)
0.002
—
710
MHz
Input Clocks (CKIN1, CKIN2, CKIN3, CKIN4)
Differential Voltage Swing
Common Mode Voltage
CKN_DPP
CKN_VCM
1.8 V ±10%
2.5 V ±10%
0.25
—
0.9
—
1.0
—
1.9
V_PP
1.4
V
1.7
V
Rise/Fall Time
Duty Cycle
CKN_TRF
CKN_DC
20–80%
Whichever is less
—
—
11
ns
40
—
60
%
50
—
—
ns
Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing.
2
Preliminary Rev. 0.3