SI5368 Datasheet, PDF (3/18 Pages) Silicon Laboratories – ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5368
Table 1. Performance Specifications (Continued)
(V_DD = 1.8 or 2.5 V ±10%, T_A = –40 to 85 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
Output Clocks (CKOUT1, CKOUT2, CKOUT3, CKOUT4, CKOUT5/FS_OUT)
Common Mode
Differential Output Swing
Single Ended Output Swing
PLL Performance
V_OCM
V_OD
V_SE
LVPECL
100 Ω load
line-to-line
V_DD – 1.42 — V_DD – 1.25 V
1.1
—
1.9
V_DD
0.5
—
0.93
Vpp
Jitter Generation
J_GEN
f_OUT = 622.08 MHz,
LVPECL output format
50 kHz–80 MHz
—
0.3
TBD ps rms
12 kHz–20 MHz
—
0.3
TBD ps rms
Jitter Transfer
External Reference Jitter
Transfer
J_PK
J_PKEXTN
—
0.05
0.1
dB
—
TBD TBD
dB
Phase Noise
CKO_PN
f_OUT = 622.08 MHz
100 Hz offset
—
TBD TBD dBc/Hz
1 kHz offset
—
TBD TBD dBc/Hz
10 kHz offset
—
TBD TBD dBc/Hz
100 kHz offset
—
TBD TBD dBc/Hz
1 MHz offset
—
TBD TBD dBc/Hz
Subharmonic Noise
Spurious Noise
SP_SUBH Phase Noise @ 100 kHz Offset —
SP_SPUR
Max spur @ n x F3
—
(n > 1, n x F3 < 100 MHz)
TBD
TBD
dBc
TBD
TBD
dBc
Package
Thermal Resistance Junction θ_JA
to Ambient
Still Air
—
40
—
ºC/W
Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing.
Preliminary Rev. 0.3
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