SI5368 Datasheet, PDF (11/18 Pages) Silicon Laboratories – ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5368
Table 3. Si5368 Pin Descriptions (Continued)
Pin #
Pin Name I/O Signal Level
Description
55
INC
I LVCMOS Coarse Latency Increment.
A pulse on this pin increases the input to output device latency
by 1/fOSC (approximately 200 ps). Detailed operations and tim-
ing characteristics for this pin may be found in the Any-Rate
Precision Clock Family Reference Manual. There is no limit on
the range of latency adjustment by this method. Pin control is
enabled by setting INCDEC_PIN = 1 (default).
If INCDEC_PIN = 0, this pin is ignored and coarse output
latency is controlled via the CLAT register.
If both INC and DEC are tied high, phase buildout is disabled
and the device maintains a fixed-phase relationship between
the selected input clock and the output clock during an input
clock switch. Detailed operations and timing characteristics for
these pins may be found in the Any-Rate Precision Clock Fam-
ily Reference Manual.
This pin has a weak pull-down.
58
C1A
O LVCMOS CKIN1 Active Clock Indicator.
This pin serves as the CKIN1 active clock indicator. The
CK1_ACTV_REG bit always reflects the active clock status for
CKIN1. If CK1_ACTV_PIN = 1, this status will also be reflected
on the C1A pin with active polarity controlled by the
CK_ACTV_POL bit. If CK1_ACTV_PIN = 0, this output tristates.
59
C2A
O LVCMOS CKIN2 Active Clock Indicator.
This pin serves as the CKIN2 active clock indicator. The
CK2_ACTV_REG bit always reflects the active clock status for
CKIN_2. If CK2_ACTV_PIN = 1, this status will also be reflected
on the C2A pin with active polarity controlled by the
CK_ACTV_POL bit. If CK2_ACTV_PIN = 0, this output tristates.
60
SCL
I
LVCMOS Serial Clock.
This pin functions as the serial port clock input for both SPI and
I²C modes.
This pin has a weak pull-down.
61
SDA_SDO I/O LVCMOS Serial Data.
In I²C microprocessor control mode (CMODE = 0), this pin func-
tions as the bidirectional serial data port.In SPI microprocessor
control mode (CMODE = 1), this pin functions as the serial data
output.
68
A0
I LVCMOS Serial Port Address.
69
A1
In I²C microprocessor control mode (CMODE = 0), these pins
function as hardware controlled address bits. In SPI micropro-
cessor control mode (CMODE = 1), these pins are ignored.
This pin has a weak pull-down.
70
A2_SS
I LVCMOS Serial Port Address/Slave Select.
In I²C microprocessor control mode (CMODE = 0), this pin func-
tions as a hardware controlled address bit.
In SPI microprocessor control mode (CMODE = 1), this pin
functions as the slave select input.
This pin has a weak pull-down.
Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map.
Preliminary Rev. 0.3
11