SI5368 Datasheet, PDF (12/18 Pages) Silicon Laboratories – ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5368
Table 3. Si5368 Pin Descriptions (Continued)
Pin #
Pin Name I/O Signal Level
Description
71
SDI
I
LVCMOS Serial Data In.
In SPI microprocessor control mode (CMODE = 1), this pin
functions as the serial data input.
In I²C microprocessor control mode (CMODE = 0), this pin is
ignored.
This pin has a weak pull-down.
77
CKOUT3+ O
MULTI Clock Output 3.
78
CKOUT3–
Differential clock output. Output signal format is selected by
SFOUT3_REG register bits. Output is differential for LVPECL,
LVDS, and CML compatible modes. For CMOS format, both
output pins drive identical single-ended clock outputs.
82
CKOUT1– O
MULTI Clock Output 1.
83
CKOUT1+
Differential clock output. Output signal format is selected by
SFOUT1_REG register bits. Output is differential for LVPECL,
LVDS, and CML compatible modes. For CMOS format, both
output pins drive identical single-ended clock outputs.
87
FS_OUT– O
MULTI Frame Sync Output.
88
FS_OUT+
Differential frame sync output or fifth high-speed clock output.
Output signal format is selected by SFOUT_FSYNC_REG reg-
ister bits. Output is differential for LVPECL, LVDS, and CML
compatible modes. For CMOS format, both output pins drive
identical single-ended clock outputs. Duty cycle and active
polarity are controlled by FSYNC_PW and FSYNC_POL bits,
respectively. Detailed operations and timing characteristics for
these pins may be found in the Any-Rate Precision Clock Fam-
ily Reference Manual.
90
CMODE
I
LVCMOS Control Mode.
Selects I²C or SPI control mode for the device.
0 = I²C Control Mode.
1 = SPI Control Mode.
92
CKOUT2+ O
MULTI Clock Output 2.
93
CKOUT2–
Differential clock output. Output signal format is selected by
SFOUT2_REG register bits. Output is differential for LVPECL,
LVDS, and CML compatible modes. For CMOS format, both
output pins drive identical single-ended clock outputs.
97
CKOUT4– O
MULTI Clock Output 4.
98
CKOUT4+
Differential clock output. Output signal format is selected by
SFOUT4_REG register bits. Output is differential for LVPECL,
LVDS, and CML compatible modes. For CMOS format, both
output pins drive identical single-ended clock outputs.
GND PAD GND PAD GND
Supply
Ground Pad.
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map.
12
Preliminary Rev. 0.3