SI53322 Datasheet, PDF (7/22 Pages) Silicon Laboratories – 1:2 LOW JITTER LVPECL CLOCK BUFFER

Si53322
2. Functional Description
The Si53322 is a low-jitter, low-skew 1:2 LVPECL buffer. The device has a universal input that accepts most
common differential or LVCMOS input signals.
2.1. Universal, Any-Format Input
The universal input stage enables simple interfacing to a wide variety of clock formats, including LVPECL, low-
power LVPECL, LVCMOS, LVDS, HCSL, and CML. Tables 10 and 11 summarize the various ac- and dc-coupling
options supported by the device. For the best high-speed performance, the use of differential formats is
recommended. For both single-ended and differential input clocks, the fastest possible slew rate is recommended
as low slew rates can increase the noise floor and degrade jitter performance. Though not required, a minimum
slew rate of 0.75 V/ns is recommended for differential formats and 1.0 V/ns for single-ended formats. See “AN766:
Understanding and Optimizing Clock Buffer’s Additive Jitter Performance” for more information.
Table 10. LVPECL, LVCMOS, and LVDS Input Clock Options
1.8 V
2.5/3.3 V
LVPECL
AC-Couple DC-Couple
N/A
N/A
Yes
Yes
LVCMOS
AC-Couple DC-Couple
No
No
No
Yes
LVDS
AC-Couple DC-Couple
Yes
No
Yes
Yes
Table 11. HCSL and CML Input Clock Options
1.8 V
2.5/3.3 V
HCSL
AC-Couple DC-Couple
No
No
Yes (3.3 V) Yes (3.3 V)
CML
AC-Couple DC-Couple
Yes
No
Yes
No
0.1 µF
CLKx
Si533xx
100 
/CLKx
0.1 µF
Figure 2. Differential HCSL, LVPECL, Low-Power LVPECL, LVDS, CML AC-Coupled Input
Termination
VDD _{= 3.3 V or 2.5 V}
CMOS
Driver
Rs
V_DD
1 k
V_DD
Si533xx
CLKx
50
/CLKx
V_TERM = V_DD/2
1 k
VREF
Figure 3. LVCMOS DC-Coupled Input Termination
Rev. 1.0
7