SI53322 Datasheet, PDF (5/22 Pages) Silicon Laboratories – 1:2 LOW JITTER LVPECL CLOCK BUFFER

Si53322
Table 6. Additive Jitter, Differential Clock Input
V_DD
Input^1,2
Output
Additive Jitter
(fs rms, 12 kHz to
20 MHz)³
Freq Clock Format Amplitude
Differential Clock Format
Typ
Max
(MHz)
V_IN
20%-80% Slew
(Single-Ended, ^{Rate (V/ns)}
Peak-to-Peak)
3.3
725
Differential
0.15
0.637
LVPECL
55
95
3.3 156.25 Differential
0.5
0.458
LVPECL
160
185
2.5
725
Differential
0.15
0.637
LVPECL
55
95
2.5 156.25 Differential
0.5
0.458
LVPECL
145
185
Notes:
1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock
Buffer’s Additive Jitter Performance” for more information.
2. AC-coupled differential inputs.
3. Measured differentially using a balun at the phase noise analyzer input. See Figure 1.
Table 7. Additive Jitter, Single-Ended Clock Input
V_DD
Input^1,2
Output
Additive Jitter
(fs rms, 12 kHz to
20 MHz)³
Freq Clock Format Amplitude SE 20%-80% Clock Format
Typ
Max
(MHz)
V_IN
(single-ended,
Slew Rate
(V/ns)
peak to peak)
3.3 156.25 Single-ended
2.18
1
LVPECL
160
185
2.5 156.25 Single-ended
2.18
1
LVPECL
145
185
Notes:
1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock
Buffer’s Additive Jitter Performance” for more information.
2. DC-coupled single-ended inputs.
3. Measured differentially using a balun at the phase noise analyzer input. See Figure 1.
CLK SYNTH
SMA103A
PSPL 5310A
Balun
CLKx
Si533xx
50
DUT
50
/CLKx
PSPL 5310A
Balun
AG E5052 Phase Noise
Analyzer
50ohm
Figure 1. Differential Measurement Method Using a Balun
Rev. 1.0
5